[Linaro-uefi,linaro-uefi,v1,08/32] Hisilicon/D05: Uncore PMU: Add DDRC PMU device and properties

Message ID 1505829398-52214-9-git-send-email-heyi.guo@linaro.org
State New
Headers show
Series
  • Update D03/D05 binary for edk update and fix some error.
Related show

Commit Message

Guo Heyi Sept. 19, 2017, 1:56 p.m.
From: Chenhui Sun <sunchenhui@huawei.com>

Use _HID of HISI0232 for DDRC uncore PMU in hi1616 Every CPU die
support 2 DDRC channels and each DDRC channel will be represented
as a device with _HID and _UID.
The device will also support _STA method.

Signed-off-by: Anurup M <anurup.m@huawei.com>
---
 .../Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl     | 272 +++++++++++++++++++++
 1 file changed, 272 insertions(+)

Patch

diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl
index d2a1432..dcb287d 100644
--- a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05UncorePmu.asl
@@ -382,4 +382,276 @@  Scope(_SB) {
       })
     }
   }
+
+  // DDRC Channel 0 for CPU die #1 (scl #1)
+  Device (DDR0) {
+    Name (_HID, "HISI0232")  // _HID: Hardware ID
+    Name (_UID, 0)  // _UID: Unique ID
+    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+      QWordMemory (
+        ResourceProducer,
+        PosDecode,
+        MinFixed,
+        MaxFixed,
+        NonCacheable,
+        ReadWrite,
+        0x0, // Granularity
+        0x40348000, // Min Base Address
+        0x40348FFF, // Max Base Address
+        0x0, // Translate
+        0x1000 // Length
+      )
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"hisilicon,scl-id", 0x01},
+        Package () {"hisilicon,ch-id", 0x00},
+      }
+    })
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0xf)
+    }
+  }
+
+  // DDRC Channel 1 for CPU die #1 (scl #1)
+  Device (DDR1) {
+    Name (_HID, "HISI0232")  // _HID: Hardware ID
+    Name (_UID, 1)  // _UID: Unique ID
+    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+      QWordMemory (
+        ResourceProducer,
+        PosDecode,
+        MinFixed,
+        MaxFixed,
+        NonCacheable,
+        ReadWrite,
+        0x0, // Granularity
+        0x40358000, // Min Base Address
+        0x40358FFF, // Max Base Address
+        0x0, // Translate
+        0x1000 // Length
+      )
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"hisilicon,scl-id", 0x01},
+        Package () {"hisilicon,ch-id", 0x01},
+      }
+    })
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0xf)
+    }
+  }
+
+  // DDRC Channel 0 for CPU die #2 (scl #3)
+  Device (DDR2) {
+    Name (_HID, "HISI0232")  // _HID: Hardware ID
+    Name (_UID, 2)  // _UID: Unique ID
+    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+      QWordMemory (
+        ResourceProducer,
+        PosDecode,
+        MinFixed,
+        MaxFixed,
+        NonCacheable,
+        ReadWrite,
+        0x0, // Granularity
+        0x60348000, // Min Base Address
+        0x60348FFF, // Max Base Address
+        0x0, // Translate
+        0x1000 // Length
+      )
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"hisilicon,scl-id", 0x03},
+        Package () {"hisilicon,ch-id", 0x00},
+      }
+    })
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0xf)
+    }
+  }
+
+  // DDRC Channel 1 for CPU die #2 (scl #3)
+  Device (DDR3) {
+    Name (_HID, "HISI0232")  // _HID: Hardware ID
+    Name (_UID, 3)  // _UID: Unique ID
+    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+      QWordMemory (
+        ResourceProducer,
+        PosDecode,
+        MinFixed,
+        MaxFixed,
+        NonCacheable,
+        ReadWrite,
+        0x0, // Granularity
+        0x60358000, // Min Base Address
+        0x60358FFF, // Max Base Address
+        0x0, // Translate
+        0x1000 // Length
+      )
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"hisilicon,scl-id", 0x03},
+        Package () {"hisilicon,ch-id", 0x01},
+      }
+    })
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0xf)
+    }
+  }
+
+  // DDRC Channel 0 for CPU die #3 (scl #5)
+  Device (DDR4) {
+    Name (_HID, "HISI0232")  // _HID: Hardware ID
+    Name (_UID, 4)  // _UID: Unique ID
+    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+      QWordMemory (
+        ResourceProducer,
+        PosDecode,
+        MinFixed,
+        MaxFixed,
+        NonCacheable,
+        ReadWrite,
+        0x0, // Granularity
+        0x40040348000, // Min Base Address
+        0x40040348FFF, // Max Base Address
+        0x0, // Translate
+        0x1000 // Length
+      )
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"hisilicon,scl-id", 0x05},
+        Package () {"hisilicon,ch-id", 0x00},
+      }
+    })
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0xf)
+    }
+  }
+
+  // DDRC Channel 1 for CPU die #3 (scl #5)
+  Device (DDR5) {
+    Name (_HID, "HISI0232")  // _HID: Hardware ID
+    Name (_UID, 5)  // _UID: Unique ID
+    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+      QWordMemory (
+        ResourceProducer,
+        PosDecode,
+        MinFixed,
+        MaxFixed,
+        NonCacheable,
+        ReadWrite,
+        0x0, // Granularity
+        0x40040358000, // Min Base Address
+        0x40040358FFF, // Max Base Address
+        0x0, // Translate
+        0x1000 // Length
+      )
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"hisilicon,scl-id", 0x05},
+        Package () {"hisilicon,ch-id", 0x01},
+      }
+    })
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0xf)
+    }
+  }
+
+  // DDRC Channel 0 for CPU die #4 (scl #7)
+  Device (DDR6) {
+    Name (_HID, "HISI0232")  // _HID: Hardware ID
+    Name (_UID, 6)  // _UID: Unique ID
+    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+      QWordMemory (
+        ResourceProducer,
+        PosDecode,
+        MinFixed,
+        MaxFixed,
+        NonCacheable,
+        ReadWrite,
+        0x0, // Granularity
+        0x40060348000, // Min Base Address
+        0x40060348FFF, // Max Base Address
+        0x0, // Translate
+        0x1000 // Length
+      )
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"hisilicon,scl-id", 0x07},
+        Package () {"hisilicon,ch-id", 0x00},
+      }
+    })
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0xf)
+    }
+  }
+
+  // DDRC Channel 1 for CPU die #4 (scl #7)
+  Device (DDR7) {
+    Name (_HID, "HISI0232")  // _HID: Hardware ID
+    Name (_UID, 7)  // _UID: Unique ID
+    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
+      QWordMemory (
+        ResourceProducer,
+        PosDecode,
+        MinFixed,
+        MaxFixed,
+        NonCacheable,
+        ReadWrite,
+        0x0, // Granularity
+        0x40060358000, // Min Base Address
+        0x40060358FFF, // Max Base Address
+        0x0, // Translate
+        0x1000 // Length
+      )
+    })
+
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"hisilicon,scl-id", 0x07},
+        Package () {"hisilicon,ch-id", 0x01},
+      }
+    })
+
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0xf)
+    }
+  }
 }