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[54.225.227.206]) by mx.google.com with ESMTP id k57si2056534qtf.10.2017.09.20.08.03.49; Wed, 20 Sep 2017 08:03:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 2639860C95; Wed, 20 Sep 2017 15:03:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 80A5960999; Wed, 20 Sep 2017 14:58:38 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 49D9A64456; Wed, 20 Sep 2017 14:58:35 +0000 (UTC) Received: from mail-pg0-f42.google.com (mail-pg0-f42.google.com [74.125.83.42]) by lists.linaro.org (Postfix) with ESMTPS id 0CFA760999 for ; Wed, 20 Sep 2017 14:56:21 +0000 (UTC) Received: by mail-pg0-f42.google.com with SMTP id j70so1803789pgc.10 for ; Wed, 20 Sep 2017 07:56:20 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AcQnNWdD0ooO/mBYeRNJBIHQmsFkBh8KN7ip30l1+iA=; b=pSOnku+VAn6zSy4lKU3fySS9dVgxImBUcMMmIe7RNcIvCNxJ9g+SJmEaZRvMEqWjKR Qe/JI52/e3e2eTmM5SrdD4jcZFEhQIN94QWf/UFiEZ/CWVFjYmsV4MxE5HmL47M6YHD5 6Cmw2gufRzNa20iOaH9+IW3IlO3BSHzwR8Bc5ucRzdqqq21JR3m0zI6AdAwngdZVcrUs lCfocaLS/W2e8JUa+xO4xI5Q+RhsyjBHjVZLjs5AkcwuT057XY9x3wYX1puv4QJT/7Mf HJvsChgQgFjn5VyHn3f5A+q8c5ML3iSNDnDjdmp1hqUPjo4sqOvqmPXhBpp5O89clbf0 TCrw== X-Gm-Message-State: AHPjjUgNfM9Z0VVBzdZoKC7XG/qiUC7g9npc2lEcC4rQKgl81sNkDak1 R4GTLec480ZrEELi7BnMPzERpYf4 X-Google-Smtp-Source: AOwi7QChXAgPqlAQH6GF9R+RCZPCtjuhtytyH5xRDRkEZqLhfrUgMn7flaxyVE7D0C8u4PmJz2ghzQ== X-Received: by 10.99.98.70 with SMTP id w67mr2497774pgb.362.1505919380308; Wed, 20 Sep 2017 07:56:20 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id c7sm9157624pfc.55.2017.09.20.07.56.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 20 Sep 2017 07:56:19 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Wed, 20 Sep 2017 22:48:58 +0800 Message-Id: <1505918938-52550-15-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505918938-52550-1-git-send-email-heyi.guo@linaro.org> References: <1505918938-52550-1-git-send-email-heyi.guo@linaro.org> Cc: Ming Huang , zhangjinsong2@huawei.com, huangming23@huawei.com, guoheyi@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v2 11/11] Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device. X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Ming Huang 1. Because Hi161x chip doesn't support "ARI Forwarding Enable" function, BIOS will enumerate 32 same devices (Device Number 0~31) when attach a Non-ARI capable device in the RP. Hi161x chip will not fix it, need BIOS patch. 2. Just enlarge iatu for those root port with ARI capable device attached, Non-ARI capable device's RP, keep iatu limitation. 3. Remove previous temporary solution as below commit id: "7d157da88852cc91df2b11b10ade2edbbfbe77da" Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jason zhang --- .../Drivers/PciHostBridgeDxe/PciHostBridge.c | 1 + .../Drivers/PciHostBridgeDxe/PciHostBridge.h | 4 ++ .../Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 76 ++++++++++++++++++++++ 3 files changed, 81 insertions(+) diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index 6ecc1e5..5bc04a2 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -839,6 +839,7 @@ NotifyPhase( case EfiPciHostBridgeEndEnumeration: PCIE_DEBUG("Case EfiPciHostBridgeEndEnumeration\n"); + EnlargeAtuConfig0 (This); break; case EfiPciHostBridgeBeginBusAllocation: diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h index cddda6b..925ed40 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h @@ -518,4 +518,8 @@ RootBridgeConstructor ( IN UINT32 Seg ); +VOID +EnlargeAtuConfig0 ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This + ); #endif diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 8dfb4b9..b41dbe2 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -14,6 +14,7 @@ **/ #include "PciHostBridge.h" +#include #include #include #include @@ -2322,3 +2323,78 @@ RootBridgeIoConfiguration ( return EFI_SUCCESS; } +BOOLEAN +PcieCheckAriFwdEn ( + UINTN PciBaseAddr + ) +{ + UINT8 PciPrimaryStatus; + UINT8 CapabilityOffset; + UINT8 CapId; + UINT8 TempData; + + PciPrimaryStatus = MmioRead16 (PciBaseAddr + PCI_PRIMARY_STATUS_OFFSET); + + if (PciPrimaryStatus & EFI_PCI_STATUS_CAPABILITY) { + CapabilityOffset = MmioRead8 (PciBaseAddr + PCI_CAPBILITY_POINTER_OFFSET); + CapabilityOffset &= ~(BIT0 | BIT1); + + while ((CapabilityOffset != 0) && (CapabilityOffset != 0xff)) { + CapId = MmioRead8 (PciBaseAddr + CapabilityOffset); + if (CapId == EFI_PCI_CAPABILITY_ID_PCIEXP) { + break; + } + CapabilityOffset = MmioRead8 (PciBaseAddr + CapabilityOffset + 1); + CapabilityOffset &= ~(BIT0 | BIT1); + } + } else { + PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); + return FALSE; + } + + if ((CapabilityOffset == 0xff) || (CapabilityOffset == 0x0)) { + PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); + return FALSE; + } + + TempData = MmioRead16 (PciBaseAddr + CapabilityOffset + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET); + TempData &= EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING; + + if (TempData == EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING) { + return TRUE; + } else { + return FALSE; + } +} + +VOID +EnlargeAtuConfig0 ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This + ) +{ + UINTN RbPciBase; + UINT64 MemLimit; + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + + PCIE_DEBUG ("In Enlarge RP iatu Config 0.\n"); + + HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List = HostBridgeInstance->Head.ForwardLink; + + while (List != &HostBridgeInstance->Head) { + PCIE_DEBUG ("HostBridge has data.\n"); + RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + + RbPciBase = RootBridgeInstance->RbPciBar; + + // Those ARI FWD Enable Root Bridge, need enlarge iatu window. + if (PcieCheckAriFwdEn (RbPciBase)) { + MemLimit = GetPcieCfgAddress (RootBridgeInstance->Ecam, RootBridgeInstance->BusBase + 2, 0, 0, 0) - 1; + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, 1); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit); + } + List = List->ForwardLink; + } +}