From patchwork Thu Sep 21 15:22:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113276 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2159712qgf; Thu, 21 Sep 2017 08:27:38 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBC7b+H96Wo4vb2lRI35+5wcmEMrEdGoND7vKSd6VwdjzXyUsxnVl7X0BcFDGfDXeB5n8/C X-Received: by 10.80.212.40 with SMTP id t40mr1627732edh.67.1506007658457; Thu, 21 Sep 2017 08:27:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506007658; cv=none; d=google.com; s=arc-20160816; b=ekhYsGCXlwee5Lo5/K9ZcI0e9CLysYo7BUfWRBSsJK3EhsywV9/3l5g5P/mFkxJSXb RUYOKXCeD+VGztSE8pInLO/7X9BDIM15R1RUTuk1Jnoy17Hk3Wzw3qvcm2GSjQwq9Y5+ 4EiEQk/tE4UVC/DyBCZ9DgG+qUhO+JARTkVBT7gpuDmYFX5gp91iTnUVlkiQFnZLAOaa nH5IkMnnrEIkiNu31ApUIAe/vylY4GdQSVQnp8N/lo4hT/G/Ojlrr4EY65vpEYknNv6k AqbtLNRaJmHhq8TBCrPagjzLOGgMFcnx1WX6WeArOCI5sn9c6SLjzc+sQAulDT58Pxxq XzJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=yh98QEK3t9aVJW4a/JQln3tZh7tWAzQetAft3LyV9I0=; b=hpi7rzrOJk79kYkjlrjsJM88FQyaDyzl0LQA6OD/a56cYypyTDMvGCscsUbWIp9+Au kNaWkr2RK8w7l8sVaAv5a9d8VxjE2Cl5xBbN2/zx12HP3XvD0E4GpmG5qFAaWmgIfoYv bfdITfCrdMvmLCkmmxcl+jinsqI4onkFRV7KCB5OS3hNJISoRDSpml3aQT1Z2JhjNkEn lAaFjOiQ25DwjpMp/z/6yLppJ5WImmlL0Rrx3OVkS7/kIvUJRz9SPp30CfJm7Um60Snq 4zNjXlYRgB75AgjVm4tA1+RPtxQis+JZ9lrHfbIAPtQrdrZN3pv0Qy7+TC/GaZxkrzN0 V9cw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=y6+7Mhoy; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id c3si1825406edc.15.2017.09.21.08.27.38; Thu, 21 Sep 2017 08:27:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=y6+7Mhoy; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 08DABC2208E; Thu, 21 Sep 2017 15:23:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 58500C22068; Thu, 21 Sep 2017 15:23:21 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1C7DCC21FD0; Thu, 21 Sep 2017 15:22:58 +0000 (UTC) Received: from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17]) by lists.denx.de (Postfix) with ESMTPS id 7B482C2203F for ; Thu, 21 Sep 2017 15:22:54 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMqoH010598; Thu, 21 Sep 2017 10:22:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007372; bh=92M/OmzV5qovTuXugUlI8oC6LFq00Y4thloiiCM0MK4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=y6+7MhoyCkXW8sE1zYLZpcxbeg+PmpN3SP5CsdBTxnRgWq552mgElqnd5IhXJNaxY GEWneG78RJCcop5HG6vDui8iSQ7G/ToPqL7tlC0kZRAoq5XJDrQ2EvwOyDWXMv+H1A zAfBg8OY2jQSaqUW0Dbn7HyEXXIZjl7fBAxrcYR4= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMq4s009461; Thu, 21 Sep 2017 10:22:52 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:22:52 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:22:52 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMp3x020830; Thu, 21 Sep 2017 10:22:51 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:13 +0200 Message-ID: <1506007346-10037-11-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 10/23] ARM: OMAP5/DRA7: Enable iodelay recalibration to be done from uboot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Add a new API to perform iodelay recalibration without isolate io to be used in uboot. The data manual of J6/J6 Eco recommends to set different IODELAY values depending on the mode in which the MMC/SD is enumerated in order to ensure IO timings are met. The MMC driver can use the new API to set the IO delay values depending on the MMC mode. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h | 3 +++ arch/arm/mach-omap2/omap5/dra7xx_iodelay.c | 30 ++++++++++++++++++++++++ include/configs/am57xx_evm.h | 2 -- include/configs/dra7xx_evm.h | 2 -- 4 files changed, 33 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h index c997004..a8780ee 100644 --- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h +++ b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h @@ -83,6 +83,9 @@ void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, struct iodelay_cfg_entry const *iodelay, int niodelays); +void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, + struct iodelay_cfg_entry const *iodelay, + int niodelays); int __recalibrate_iodelay_start(void); void __recalibrate_iodelay_end(int ret); diff --git a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c index 8798730..a9a9f75 100644 --- a/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c +++ b/arch/arm/mach-omap2/omap5/dra7xx_iodelay.c @@ -272,3 +272,33 @@ err: __recalibrate_iodelay_end(ret); } + +void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads, + struct iodelay_cfg_entry const *iodelay, + int niodelays) +{ + int ret = 0; + + /* unlock IODELAY CONFIG registers */ + writel(CFG_IODELAY_UNLOCK_KEY, (*ctrl)->iodelay_config_base + + CFG_REG_8_OFFSET); + + ret = calibrate_iodelay((*ctrl)->iodelay_config_base); + if (ret) + goto err; + + ret = update_delay_mechanism((*ctrl)->iodelay_config_base); + + /* Configure Mux settings */ + do_set_mux32((*ctrl)->control_padconf_core_base, pad, npads); + + /* Configure Manual IO timing modes */ + ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); + if (ret) + goto err; + +err: + /* lock IODELAY CONFIG registers */ + writel(CFG_IODELAY_LOCK_KEY, (*ctrl)->iodelay_config_base + + CFG_REG_8_OFFSET); +} diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h index 0c70c53..4125391 100644 --- a/include/configs/am57xx_evm.h +++ b/include/configs/am57xx_evm.h @@ -15,9 +15,7 @@ #include #include -#ifdef CONFIG_SPL_BUILD #define CONFIG_IODELAY_RECALIBRATION -#endif #define CONFIG_NR_DRAM_BANKS 2 diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 6c0fc35..435284a 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -14,9 +14,7 @@ #include -#ifdef CONFIG_SPL_BUILD #define CONFIG_IODELAY_RECALIBRATION -#endif #define CONFIG_VERY_BIG_RAM #define CONFIG_NR_DRAM_BANKS 2