From patchwork Thu Sep 21 15:22:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113279 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2166251qgf; Thu, 21 Sep 2017 08:33:23 -0700 (PDT) X-Google-Smtp-Source: AOwi7QAZtWIlzdRbsSgFis3huBWTVuo7r+5XU/Th2aA6cCLTfbGAfqCZWeQ9XJUZ9c5GpizOcAn9 X-Received: by 10.80.134.183 with SMTP id r52mr1637214eda.152.1506008003341; Thu, 21 Sep 2017 08:33:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506008003; cv=none; d=google.com; s=arc-20160816; b=hHNNDat7cMsIIEGq9chzqShxZLBg/YCieQxsZPktQTSXy5woGUMhC4Gg8HgpYlb/WK HUL93xmfN1Opey+HNxWtuG8fpy144hk4TVVGUJ6516G2u7ifHLIRHMNL1sNLZc4yB/T/ l7T5qcFqRhDPXmtb/W2PZruxLno64xeGeG68er+SedcfjfSb8p6jVJKKVP6uvMc8POpp inZz8e6keMm56dKX4DACUZHuYn//licFLPQFTx2+iupy+9IAtwNLrlFhL9UR3aeHo+Lw o0gXzPjQgSwwDxGVrd3TfWSSpq+foGrgzFldfXuyEXnUQvE7z7k8B4THz7p3hjHZBZbe fZAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=7aoiF8lyLtTv2y/xBOY+fXr5hJcbpYrQ5gmX2hFvMG8=; b=ECdP1BfqfCeFvx1IuzvWzb8eZzqeN7zvUbznkzU2w6hR4aklpA+RF28vLmgrUkkkQ4 /xEVw/rCxs5srlDnbjubaKkKd1GeIc7ooa9Llx049rOE34odYH6RlJfe5fabCSi1xzLA 5KN9w9MQo+WZcwK7IGoKiWKNOO84AxVY9uD/7Vf9Pi5BggzhnV8dmTj13RSsKaXBXVgD G6nWaDFSPN2f1yDjty8EM5whbe2csj+6imD/4aOwmtb0Ne0XitPkAzTQ6bc9BAUR3mCT fz20RpALz4wwZXvMQbA3h8RZSWH8ADbtHHPVmzEuG2lmxekZvxVNEdYWlngOAOYqQsWi W2/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=b3s6/zP/; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id t2si1082219edj.454.2017.09.21.08.33.23; Thu, 21 Sep 2017 08:33:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=b3s6/zP/; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id EC4B8C21FED; Thu, 21 Sep 2017 15:26:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E115CC22033; Thu, 21 Sep 2017 15:25:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E7083C22046; Thu, 21 Sep 2017 15:23:15 +0000 (UTC) Received: from fllnx210.ext.ti.com (fllnx210.ext.ti.com [198.47.19.17]) by lists.denx.de (Postfix) with ESMTPS id 1B38EC21FD0 for ; Thu, 21 Sep 2017 15:23:10 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFN9X4010637; Thu, 21 Sep 2017 10:23:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007389; bh=5LOHNyz7V5DiDn8LO4y4svg6Dg0kNsG4QjyB+UbkzXg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=b3s6/zP/b6yJU/AdjyI46eM/iUORHYdwLbvp/VsnAaXsfqc6VICbVzlzJ9XQGhtJ1 dPW705h/s01HElEHYOb8TemFTV0+TaqWvxu8RUN1IawaC2o1XvsyF3utUVNfTg2uLA LAfcs1aTq3gX6In3jK+bdoTb25MPZ0MCmrcUv9Lo= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFN9dk001141; Thu, 21 Sep 2017 10:23:09 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:23:08 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:23:08 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFN8TM023372; Thu, 21 Sep 2017 10:23:08 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:26 +0200 Message-ID: <1506007346-10037-24-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 23/23] ARM: DRA7x/AM57x: Add MMC/SD fixups for rev1.0 and rev 1.1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Since DRA7xx/AM57xx SR1.1 and SR1.0 has errata to limit the frequency of MMC1 to 96MHz and frequency of MMC2 to 48MHz for AM572x SR1.1, limit the frequency and disable higher speed modes for those revision. Also use the recommended IO delays (those tagged with "rev11") Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- board/ti/am57xx/board.c | 30 ++++++++++++++++++++++++++++++ board/ti/dra7xx/evm.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index f79aefd..4f2f8ef 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "../common/board_detect.h" #include "mux_data.h" @@ -762,6 +763,35 @@ int board_mmc_init(bd_t *bis) omap_mmc_init(1, 0, 0, -1, -1); return 0; } + +static const struct mmc_platform_fixups am57x_es1_1_mmc1_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104), + .max_freq = 96000000, +}; + +static const struct mmc_platform_fixups am57x_es1_1_mmc23_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104) | + MMC_CAP(UHS_SDR50), + .max_freq = 48000000, +}; + +const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) +{ + switch (omap_revision()) { + case DRA752_ES1_0: + case DRA752_ES1_1: + if (addr == OMAP_HSMMC1_BASE) + return &am57x_es1_1_mmc1_fixups; + else + return &am57x_es1_1_mmc23_fixups; + default: + return NULL; + } +} #endif #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 97aae01..f82e4c0 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -846,6 +846,35 @@ void board_mmc_poweron_ldo(uint voltage) palmas_mmc1_poweron_ldo(LDO1_VOLTAGE, LDO1_CTRL, voltage); } } + +static const struct mmc_platform_fixups dra7x_es1_1_mmc1_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104), + .max_freq = 96000000, +}; + +static const struct mmc_platform_fixups dra7x_es1_1_mmc23_fixups = { + .hw_rev = "rev11", + .unsupported_caps = MMC_CAP(MMC_HS_200) | + MMC_CAP(UHS_SDR104) | + MMC_CAP(UHS_SDR50), + .max_freq = 48000000, +}; + +const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr) +{ + switch (omap_revision()) { + case DRA752_ES1_0: + case DRA752_ES1_1: + if (addr == OMAP_HSMMC1_BASE) + return &dra7x_es1_1_mmc1_fixups; + else + return &dra7x_es1_1_mmc23_fixups; + default: + return NULL; + } +} #endif #ifdef CONFIG_USB_DWC3