From patchwork Thu Sep 21 15:22:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113281 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2166750qgf; Thu, 21 Sep 2017 08:33:50 -0700 (PDT) X-Google-Smtp-Source: AOwi7QA5DCbH29fQU3JEemI9UMVIuJTmSB12ZK4PU5Qbe4yvggkLqZin8wehmqQJ4+6B9lGyS0q+ X-Received: by 10.80.165.141 with SMTP id a13mr1591641edc.200.1506008030202; Thu, 21 Sep 2017 08:33:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506008030; cv=none; d=google.com; s=arc-20160816; b=ZcZgwya0E3/RYQglhMhaFLtnXowhIYIcB4+1qYIW6KyZxtESPy6Stb7X4zJhKB7J/8 Fh5nW8QeVXzttHpIoBDaaZCJbQ/nQtik7BphUj1uLQ554QLmIxVIsIa8AyUmZnhnp9Ju +Qgx4wgSIZ8j4tmfzCg8SjAIJqyBvSCe3j9CTxzLZKrT2aj2bPO6n3P2FfsyCyIzKBQZ /0k4uyCg0dmw0wAcTlwX4S20wvsEmQQW8/F4sgKxAmGh04Anf6lUh61ADdPrJP4Xlu77 wx09/Xa717N+4p8Npa41SUzd9QndXSm+p+kIXQm8lvfPOVLudGIjsLpeTOr+A/K7yN4X Ie7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=Vhn58FU7g6bzwH7W8juxiV0YFJ61+hhVvKdTyPRIM/o=; b=0aIAv7F48okMzQuWjDbtriiRizi8xYmaOU73cFcBDYBa3mub04VsQyoMWO+vTeWT0Z qTjTlL55L6wSYFrXrBPymQXMc3Y4kYI90zzsGc8a8x7h+Q4uEjjgEYB2P5+uvIyYqVwA PlKGJMHQJ7x3fpY3Y5T3C5EKs3skbFylCaPhZG4nvsbpNzP83PJyaJ816pP0DliXiP0m GVuA9gUAwhnNehU81WCHrIyDTiyDeoqanxWRMrtZ7pdBF1/23GKPI/IW3Hqo6qemSIjJ /JPPSkEzsGjtwGf5UB96jzoX+Yi3MfKiLLZUQApocvAXmr1C3V2taeUcuX+NqdRH+C56 Z/Og== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=qWgCHM0O; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 92si623767edn.391.2017.09.21.08.33.49; Thu, 21 Sep 2017 08:33:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=qWgCHM0O; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id D9151C220EC; Thu, 21 Sep 2017 15:26:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2A7DEC21FFE; Thu, 21 Sep 2017 15:24:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 45E0DC21E5B; Thu, 21 Sep 2017 15:23:06 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id 4C2F7C2203F for ; Thu, 21 Sep 2017 15:23:02 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFN0Pm007954; Thu, 21 Sep 2017 10:23:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007380; bh=oLkroCB5WIGj/iPoCXrGFfaWlC1lPrmyV67J/DAaKOA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qWgCHM0OC0Jq+jFcLiZlb5M24AcSbLqAUpVGRBKkaKw3fnO5b0LOeOjrlyp8Lw4Pk ff1/ZnSm7gg9SDBsZdWiTYlJcxBKZJ5qmQa1DxD+Rd85BJSUUu9gJuka1BLADvUlt7 XOReQTf2BAGMWUQgaAvxSVhi1JrYkJKy6X/iSXjA= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFN0f1000595; Thu, 21 Sep 2017 10:23:00 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:23:00 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:22:59 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMxjf020995; Thu, 21 Sep 2017 10:22:59 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:19 +0200 Message-ID: <1506007346-10037-17-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 16/23] mmc: omap_hsmmc: allow mmc clock to be gated X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I mmc core has defined a new parameter *clk_disable* to gate the clock. Disable the clock here if *clk_disable* is set. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- drivers/mmc/omap_hsmmc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 0a4f8a7..f3da446 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -1203,6 +1203,7 @@ static int omap_hsmmc_set_ios(struct udevice *dev) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct mmc *mmc = upriv->mmc; #endif + struct hsmmc *mmc_base = priv->base_addr; if (priv->bus_width != mmc->bus_width) omap_hsmmc_set_bus_width(mmc); @@ -1210,6 +1211,11 @@ static int omap_hsmmc_set_ios(struct udevice *dev) if (priv->clock != mmc->clock) omap_hsmmc_set_clock(mmc); + if (mmc->clk_disable) + omap_hsmmc_stop_clock(mmc_base); + else + omap_hsmmc_start_clock(mmc_base); + #if CONFIG_IS_ENABLED(DM_MMC) if (priv->mode != mmc->selected_mode) omap_hsmmc_set_timing(mmc);