[18/23] ARM: OMAP5: set mmc clock frequency to 192MHz

Message ID	1506007346-10037-19-git-send-email-jjhiblot@ti.com
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; From: Jean-Jacques Hiblot <jjhiblot@ti.com> To: <jh80.chung@samsung.com>, <trini@konsulko.com>, <kishon@ti.com>, <sjg@chromium.org>, <lokeshvutla@ti.com> Date: Thu, 21 Sep 2017 17:22:21 +0200 Message-ID: <1506007346-10037-19-git-send-email-jjhiblot@ti.com> In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 18/23] ARM: OMAP5: set mmc clock frequency to 192MHz Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	[01/23] mmc: omap_hsmmc: cleanup clock configuration \| expand [01/23] mmc: omap_hsmmc: cleanup clock configuration [02/23] mmc: omap_hsmmc: cleanup omap_hsmmc_set_ios [03/23] mmc: omap_hsmmc: add support to set default io voltage [04/23] mmc: omap_hsmmc: set MMC mode in the UHSMS bit field [05/23] mmc: omap_hsmmc: Enable DDR mode support [06/23] mmc: omap_hsmmc: Add tuning support [07/23] mmc: omap_hsmmc: Workaround for errata id i802 [09/23] mmc: omap_hsmmc: use mmc_of_parse to populate mmc_config [10/23] ARM: OMAP5/DRA7: Enable iodelay recalibration to be done from uboot [11/23] mmc: omap_hsmmc: Add support to set IODELAY values [12/23] mmc: omap_hsmmc: Add support to get pinctrl values and max frequency for different hw rev... [16/23] mmc: omap_hsmmc: allow mmc clock to be gated [18/23] ARM: OMAP5: set mmc clock frequency to 192MHz [19/23] ARM: dts: DRA7: use new dra7-specific compatible string [23/23] ARM: DRA7x/AM57x: Add MMC/SD fixups for rev1.0 and rev 1.1

Message ID

1506007346-10037-19-git-send-email-jjhiblot@ti.com

State

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Received-SPF: pass (google.com: best guess record for domain of
	u-boot-bounces@lists.denx.de designates 81.169.180.215 as
	permitted sender) client-ip=81.169.180.215; 
From: Jean-Jacques Hiblot <jjhiblot@ti.com>
To: <jh80.chung@samsung.com>, <trini@konsulko.com>, <kishon@ti.com>,
	<sjg@chromium.org>, <lokeshvutla@ti.com>
Date: Thu, 21 Sep 2017 17:22:21 +0200
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Subject: [U-Boot] [PATCH 18/23] ARM: OMAP5: set mmc clock frequency to 192MHz
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Series

[01/23] mmc: omap_hsmmc: cleanup clock configuration | expand

Commit Message

Jean-Jacques Hiblot Sept. 21, 2017, 3:22 p.m. UTC

From: Kishon Vijay Abraham I <kishon@ti.com>

Now that omap_hsmmc has support for hs200 mode, change the clock
frequency to 192MHz. Also change the REFERENCE CLOCK frequency to
192MHz based on which the internal mmc clock divider is calculated.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
---
 arch/arm/include/asm/arch-omap5/clock.h |  2 +-
 arch/arm/include/asm/omap_mmc.h         |  4 ++++
 arch/arm/mach-omap2/omap5/hw_data.c     | 10 +++++-----
 3 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index ee2e78b..3d718c0 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -135,7 +135,7 @@ 
 
 /* CM_L3INIT_HSMMCn_CLKCTRL */
 #define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
-#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK		(1 << 25)
+#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK		(3 << 25)
 
 /* CM_L3INIT_SATA_CLKCTRL */
 #define SATA_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 6871f54..d604b79 100644
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -199,7 +199,11 @@  struct omap_hsmmc_plat {
 #define MMC_CMD0	(INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
 
 /* Clock Configurations and Macros */
+#ifdef CONFIG_OMAP54XX
+#define MMC_CLOCK_REFERENCE	192 /* MHz */
+#else
 #define MMC_CLOCK_REFERENCE	96 /* MHz */
+#endif
 
 /* DLL */
 #define DLL_SWT			(1 << 20)
diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c
index 3bdb114..30e3b68 100644
--- a/arch/arm/mach-omap2/omap5/hw_data.c
+++ b/arch/arm/mach-omap2/omap5/hw_data.c
@@ -438,17 +438,17 @@  void enable_basic_clocks(void)
 	setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
 			GPIO4_CLKCTRL_OPTFCLKEN_MASK);
 
-	/* Enable 96 MHz clock for MMC1 & MMC2 */
+	/* Enable 192 MHz clock for MMC1 & MMC2 */
 	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
 			HSMMC_CLKCTRL_CLKSEL_MASK);
 	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
 			HSMMC_CLKCTRL_CLKSEL_MASK);
 
 	/* Set the correct clock dividers for mmc */
-	setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
-			HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
-	setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
-			HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+	clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
+		     HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
+	clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
+		     HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
 
 	/* Select 32KHz clock as the source of GPTIMER1 */
 	setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,

[18/23] ARM: OMAP5: set mmc clock frequency to 192MHz

Commit Message

Patch