From patchwork Thu Sep 21 15:22:21 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113284 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2169994qgf; Thu, 21 Sep 2017 08:37:01 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDj2LFYuW8O8Xi/p2lkQX19DXwXr9bfDTj41ZTgCCcANAJpNnnWEt5oGnSeI/LbxWjQTdpg X-Received: by 10.80.144.242 with SMTP id d47mr1624499eda.79.1506008221820; Thu, 21 Sep 2017 08:37:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506008221; cv=none; d=google.com; s=arc-20160816; b=VEdyxO+Y84mwKgv6lczklFz8s968D+iTBJZBfbaxt5nmOsNsF04nt2Byhl8jvlG1Yn MfqTVv4ECyEo0Xz2eA2FSR8DrkczYP2mqxnt3G8M5I3wXuUzRRe4ZEKEFO4DGVOqs6Tw ej7bJx3cmhz5PKYvbN0vlY9OWnhClImBZxZaDVZAJtZy5GQ7frYloZdcGccDsdzKi0BB 34N6fKYELf1IjQFcC0FHPiRUwEPbk+2MiZLN8sX7Rsmba9gE0NLnV74FOn3OBzFE9laY LnweE9ntXkKus5twMX0ESyuIcKKYEoElrhAxvo/seUMwbODafQDZBP08GyR3/N4kYl0A d+6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=EO1XApAFEMvQwlI2hWs26o2YeEkoF8gIov2I52NMPD8=; b=WDyNkOjDm/OCv8PKhZ5f5zUFXqJkn/7hpcmztxWfrcjyIM9/iHqe4tc4q4dTVRDLMr 7g7TOIV5p44EoiXejb7P6MobOFVzGm92ONjqVD9zPnxeCX+o2WFoEy4A+beq73jA0WP3 nS30B2WfynTNOU59Z5eluBgKO45umva9jWcYqTrTVcusc7B6TExiF5VSlsIOijz7YKIM NwAwTFr/7UjK6kIVULTITI+aqNqTjGHsAnx2LgldU8VHnhpkLrWh2MQMH/1KVJxmztPi rYzAyqVDJfhUcIL0Yfm3SMHzJi3Q4Y/IDw6PSrtJ5fN544kXLHFIdgKWbl3WDrDOFhXp 5TRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=vjqWAi0e; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id 33si1667962edy.409.2017.09.21.08.37.01; Thu, 21 Sep 2017 08:37:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=vjqWAi0e; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 62143C220E1; Thu, 21 Sep 2017 15:32:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E5E71C220D7; Thu, 21 Sep 2017 15:32:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B997AC220CD; Thu, 21 Sep 2017 15:24:13 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id 12D56C21E28 for ; Thu, 21 Sep 2017 15:24:09 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFN7w5009167; Thu, 21 Sep 2017 10:23:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007387; bh=Bf1kAeT4yEpPcezYK2+RzwF+dxoz6wSXrGVeBn2s9ro=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vjqWAi0etdowOHB8nMMEntPG4XtJTR9NRPCQ08tZHiz5HKnQN4VhmLWXsA8Gz7muK Q52iN3T+y63ddq9xM8CQNXmugJCqLrL1OhIPlf2P3nCsVAa9NL/L+m/ZjKzNyEW5Bs yuIpAqdWjB9ukCupS4F+a7l6lcjXy7NNK/jd9Lps= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFN2gi009860; Thu, 21 Sep 2017 10:23:02 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:23:02 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:23:02 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFN1ni015099; Thu, 21 Sep 2017 10:23:02 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:21 +0200 Message-ID: <1506007346-10037-19-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 18/23] ARM: OMAP5: set mmc clock frequency to 192MHz X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I Now that omap_hsmmc has support for hs200 mode, change the clock frequency to 192MHz. Also change the REFERENCE CLOCK frequency to 192MHz based on which the internal mmc clock divider is calculated. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/arch-omap5/clock.h | 2 +- arch/arm/include/asm/omap_mmc.h | 4 ++++ arch/arm/mach-omap2/omap5/hw_data.c | 10 +++++----- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index ee2e78b..3d718c0 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -135,7 +135,7 @@ /* CM_L3INIT_HSMMCn_CLKCTRL */ #define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24) -#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25) +#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25) /* CM_L3INIT_SATA_CLKCTRL */ #define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 6871f54..d604b79 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -199,7 +199,11 @@ struct omap_hsmmc_plat { #define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) /* Clock Configurations and Macros */ +#ifdef CONFIG_OMAP54XX +#define MMC_CLOCK_REFERENCE 192 /* MHz */ +#else #define MMC_CLOCK_REFERENCE 96 /* MHz */ +#endif /* DLL */ #define DLL_SWT (1 << 20) diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index 3bdb114..30e3b68 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -438,17 +438,17 @@ void enable_basic_clocks(void) setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, GPIO4_CLKCTRL_OPTFCLKEN_MASK); - /* Enable 96 MHz clock for MMC1 & MMC2 */ + /* Enable 192 MHz clock for MMC1 & MMC2 */ setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, HSMMC_CLKCTRL_CLKSEL_MASK); /* Set the correct clock dividers for mmc */ - setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, - HSMMC_CLKCTRL_CLKSEL_DIV_MASK); - setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, - HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + clrbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); + clrbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, + HSMMC_CLKCTRL_CLKSEL_DIV_MASK); /* Select 32KHz clock as the source of GPTIMER1 */ setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,