From patchwork Thu Sep 21 15:22:10 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 113287 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp2170981qgf; Thu, 21 Sep 2017 08:38:01 -0700 (PDT) X-Google-Smtp-Source: AOwi7QDZidmwOqjql1egMCIvnPbtI6WFmWjpxYOJxyLkMdQxgCzAnQu6g3q1r/1yRC2w2Luk95zb X-Received: by 10.80.151.210 with SMTP id f18mr1598481edb.141.1506008281719; Thu, 21 Sep 2017 08:38:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506008281; cv=none; d=google.com; s=arc-20160816; b=KIUbdnLimKsHyCMo+D2CmPzbCR7Z01qtifdxSvcJ5naTYCSGKKA+qtlPQ59I8mOhB2 kZEpX7VLNHjqe9y31yr2jVZzFtCgYYeODQoSJk1WRzpyx/OcuxloTfLtST+ZKL6Sfz4w QqGCA/VvlB1UEe0lBtjgpk7k46qesyhz2Br0JInra6YEtFkBN5ArZIBKv8khWEXyeDU2 hskNLO5jX8QxLJ0PeghZ8wnvXIw/ERfS3IJ78/rQ5+Tm3F7WMf314mniNewHt0x33NR/ 5mW0zolwNFA1Z4q36jH8pX8qu/DgNUIeECAtcc+rZMi9zN28jaUC2KtQEE3z593WFNRV 6rnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=MX8isBdErgp5B2vMc48CunlrekPvhmJSga1qZq5MzyA=; b=MlZswkFZ6wEjFI7StT6TyqgjdFLbhYjGHfRt7iM/Kkphpp17dM5K+OzBmuCtR7uIGD Vk+9REoD8PPacJnMy04UWfE1u9Mhxzsz0prmnPAjMUUVNTrSspc663znvtG6cXhGKvxq M7qWu6PyNmMMwjEm8VjqdhMTsHwk590In+HFOvQLf6jjuNaWKeeLtcpGlJH2gQgxXi07 Zhe2O//uhjHGdPGWMG13d3GrakuxS0vM7GrVOYloslNSE2MKY1IwKEyd5TlGCC+SbEDS LWXUlusuCsq2z6bWfJEYmKsOOBJdm23hieXp15xKCvAbDCJq0KSBNBsVzsKralG9lOL0 cszA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=DmvdPdg+; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id j33si850486eda.5.2017.09.21.08.38.01; Thu, 21 Sep 2017 08:38:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=DmvdPdg+; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 36027C2209A; Thu, 21 Sep 2017 15:33:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9B90EC220C2; Thu, 21 Sep 2017 15:33:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B86CFC220BE; Thu, 21 Sep 2017 15:24:00 +0000 (UTC) Received: from fllnx209.ext.ti.com (fllnx209.ext.ti.com [198.47.19.16]) by lists.denx.de (Postfix) with ESMTPS id 56A35C2203D for ; Thu, 21 Sep 2017 15:23:56 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LFMrZf009137; Thu, 21 Sep 2017 10:22:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1506007373; bh=DZcVRjVwQzmUyTgLDhVKFenjVJKeZrWFN43MF0d2RSs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DmvdPdg+AY+nAcaU+dRyfJuBYZJmyCSHiQsL2RDERd003M3WO+zsrUCh+sVyFQfWA iKj4127+1Msph5PybcMC/d9dFeDF1IsND9Inhbm3fNJ4ohQdTrp6uK12+13Opxsg+Z 3iwQ3Rx3DATA8CVVFo5ErwuI7iHOeNKEKhqvg4dI= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMm5o000326; Thu, 21 Sep 2017 10:22:48 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Thu, 21 Sep 2017 10:22:48 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Thu, 21 Sep 2017 10:22:48 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LFMllK001053; Thu, 21 Sep 2017 10:22:48 -0500 From: Jean-Jacques Hiblot To: , , , , Date: Thu, 21 Sep 2017 17:22:10 +0200 Message-ID: <1506007346-10037-8-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> References: <1506007346-10037-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 07/23] mmc: omap_hsmmc: Workaround for errata id i802 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I According to errata i802, DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure. The DCRC interrupt, occurs when the last tuning block fails (the last ratio tested). The delay from CRC check until the interrupt is asserted is bigger than the delay until assertion of the tuning end flag. Assertion of tuning end flag is what masks the interrupts. Because of this race, an erroneous DCRC interrupt occurs. The suggested workaround is to disable DCRC interrupts during the tuning procedure which is implemented here. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/omap_mmc.h | 4 ++++ drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++++++++++---- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 0293281..0893844 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -219,6 +219,10 @@ struct omap_hsmmc_plat { #define mmc_reg_out(addr, mask, val)\ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) +#define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\ + IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\ + IE_BRR | IE_BWR | IE_TC | IE_CC) + int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, int wp_gpio); diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 321a091..8e42410 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -474,6 +474,25 @@ tuning_error: } #endif +static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd) +{ + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + struct hsmmc *mmc_base = priv->base_addr; + u32 irq_mask = INT_EN_MASK; + + /* + * TODO: Errata i802 indicates only DCRC interrupts can occur during + * tuning procedure and DCRC should be disabled. But see occurences + * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These + * interrupts occur along with BRR, so the data is actually in the + * buffer. It has to be debugged why these interrutps occur + */ + if (cmd && mmc_is_tuning_cmd(cmd->cmdidx)) + irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC); + + writel(irq_mask, &mmc_base->ie); +} + static int omap_hsmmc_init_setup(struct mmc *mmc) { struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); @@ -540,10 +559,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); - writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | - IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC | - IE_CC, &mmc_base->ie); - + mmc_enable_irq(mmc, NULL); mmc_init_stream(mmc_base); return 0; @@ -806,6 +822,8 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, #endif } + mmc_enable_irq(mmc, cmd); + writel(cmd->cmdarg, &mmc_base->arg); udelay(20); /* To fix "No status update" error on eMMC */ writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);