| Message ID | 1506670374-15689-9-git-send-email-m.szyprowski@samsung.com |
|---|---|
| State | New |
| Headers | show |
| Series | Exynos DRM: rewrite IPP subsystem and userspace API | expand |
On 09/29/2017 09:32 AM, Marek Szyprowski wrote: > From: Andrzej Pietrasiewicz <andrzej.p@samsung.com> > > TOP "aclk400_mscl" clock should be kept enabled all the time to allow > proper access to power management control for MSC power domain and > devices that are a part of it. This change is required for scaler to > work properly after domain power on/off sequence. > > Fixes: 318fa46cc60d ("clk/samsung: exynos542x: mark some clocks as critical") > Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Applied, thanks. -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 25601967d1cd..038701a2af4c 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -998,7 +998,7 @@ static void __init exynos5420_clk_sleep_init(void) {} GATE(0, "aclk400_isp", "mout_user_aclk400_isp", GATE_BUS_TOP, 16, 0, 0), GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", - GATE_BUS_TOP, 17, 0, 0), + GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0), GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",