[3/9] clk: samsung: Remove double assignment to CLK_ARM_CLK id in Exynos4 driver

Message ID 20171003100016.32029-4-m.szyprowski@samsung.com
State New
Headers show
Series
  • Various cleanups for Samsung clocks drivers
Related show

Commit Message

Marek Szyprowski Oct. 3, 2017, 10 a.m.
CLK_ARM_CLK ("armclk") clock is provided by cpu-clk subdriver, which is
instantiated after creating all divider clocks from exynos4_div_clks
array. There is no point assigning this id to "div_core2" clock and later
overwrite with proper "armcpu" clock by cpu-clk subdriver.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

---
 drivers/clk/samsung/clk-exynos4.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.14.2

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Comments

Chanwoo Choi Oct. 4, 2017, 1:42 p.m. | #1
Hi,

On Tue, Oct 3, 2017 at 7:00 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> CLK_ARM_CLK ("armclk") clock is provided by cpu-clk subdriver, which is

> instantiated after creating all divider clocks from exynos4_div_clks

> array. There is no point assigning this id to "div_core2" clock and later

> overwrite with proper "armcpu" clock by cpu-clk subdriver.

>

> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>

> ---

>  drivers/clk/samsung/clk-exynos4.c | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)

>

> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c

> index 3fbfd9ed82b7..3bd2d84b2a17 100644

> --- a/drivers/clk/samsung/clk-exynos4.c

> +++ b/drivers/clk/samsung/clk-exynos4.c

> @@ -721,7 +721,7 @@ static const struct samsung_div_clock exynos4_div_clks[] __initconst = {

>         DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),

>         DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),

>         DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),

> -       DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3),

> +       DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),

>         DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),

>         DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),

>         DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),


The exynos_register_cpu_clock() calls samsung_clk_add_lookup() which
overwrites the clk_hw. Looks good to me.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>


Additionally,
IMO, samsung_clk_add_lookup() might have to check whether
'ctx->clk_data.hws[id]' is NULL or not before adding lookup_id in
order to prevent the overwriting.

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics
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Patch

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 3fbfd9ed82b7..3bd2d84b2a17 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -721,7 +721,7 @@  static const struct samsung_div_clock exynos4_div_clks[] __initconst = {
 	DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),
 	DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),
 	DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),
-	DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3),
+	DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),
 	DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),
 	DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),
 	DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),