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[209.132.180.67]) by mx.google.com with ESMTP id x86si680652pfk.293.2017.10.05.04.43.55; Thu, 05 Oct 2017 04:43:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=awsbLV3t; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751326AbdJELny (ORCPT + 6 others); Thu, 5 Oct 2017 07:43:54 -0400 Received: from mail-wr0-f181.google.com ([209.85.128.181]:50656 "EHLO mail-wr0-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751280AbdJELnx (ORCPT ); Thu, 5 Oct 2017 07:43:53 -0400 Received: by mail-wr0-f181.google.com with SMTP id b21so10637970wrg.7 for ; Thu, 05 Oct 2017 04:43:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=6/YlAkCRbsUPQ/HDZpMp7E3oy4NL4adb4jSyO4Vf+ao=; b=awsbLV3tX3wltP2SqlzmqglrpAJ+WXvddeKp0WkZjF/skrCUbLe891fmaxJTvfCNWa t/T6s+s2HWh05j/tvIHAnBSItFh57QjpvjCskVUXrCvul9ux/gKIP9Envt9hdHI2JZfV HiGs1Btd4eF296l5X0mvhnrB8HLUqIYUig4x0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=6/YlAkCRbsUPQ/HDZpMp7E3oy4NL4adb4jSyO4Vf+ao=; b=D6VYVOAtilP9XnN0oEvmmtx6WMlFNk1QZLHlR5Z5J3f5X3GSRGwhosRvkyQ6lWquI2 QA+eez+EiXBUA0A3DdwwpGpomlp3wshqJqC5T1BjGReRRwWKICqXgyd5mmmQ7YQqkME6 pfS++2FawoccZGfTmttxbGbxm+sO8jUeTb5OJm8gy9NpOlZBtgiZmUL70NspHbOwyaAi mRjdLn87UnBHq26MT1wOIWN2yjIfRsNabG4Xy8V1HMkNlfMza24Zpxjal/GtsNKQmAWI 3o5BaEhIlwD+zE3IlrrPylwFEi07q317SwRmW4QPz5bDTzxx+bw6JO8wSq1PxQNIKqQf 4ycg== X-Gm-Message-State: AMCzsaVShMyXoJBM9TqZ2Cu6L1YP6qDwROoF2SRnqDGwPPySINz/ii3r jXxVjErR4DSrMqDTX4I0QUpk2w== X-Google-Smtp-Source: AOwi7QBydxe8vGEDk5SyO7ls7c07cxo0L+kF/5Zk8cjFewA9oZVezVJ3KHsu4bEO3CG4tY5eD5gPig== X-Received: by 10.223.156.139 with SMTP id d11mr1452260wre.214.1507203831920; Thu, 05 Oct 2017 04:43:51 -0700 (PDT) Received: from localhost.localdomain ([160.90.203.54]) by smtp.gmail.com with ESMTPSA id 10sm15841695wrt.59.2017.10.05.04.43.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Oct 2017 04:43:51 -0700 (PDT) From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com, catalin.marinas@arm.com, leif.lindholm@linaro.org, graeme.gregory@linaro.org, daniel.thompson@Linaro.org, Ard Biesheuvel Subject: [PATCH] drivers/irqchip: gicv3: add workaround for Synquacer pre-ITS Date: Thu, 5 Oct 2017 12:43:44 +0100 Message-Id: <20171005114344.21029-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Socionext Synquacer SoC's implementation of GICv3 has a so-called 'pre-ITS', which maps 32-bit writes targeted at a separate window of size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device ID taken from bits [device_id_bits + 1:2] of the window offset. Writes that target GITS_TRANSLATER directly are reported as originating from device ID #0. So add a workaround for this. Given that this breaks isolation, clear the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well. Signed-off-by: Ard Biesheuvel --- Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 4 ++ arch/arm64/Kconfig | 8 ++++ drivers/irqchip/irq-gic-v3-its.c | 50 ++++++++++++++++++-- 3 files changed, 58 insertions(+), 4 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index 4c29cdab0ea5..112ebb286728 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -75,6 +75,10 @@ These nodes must have the following properties: - reg: Specifies the base physical address and size of the ITS registers. +Optional: +- socionext,synquacer-pre-its: (u64, u64) tuple describing the PCI address + and size of the pre-ITS window. + The main GIC node must contain the appropriate #address-cells, #size-cells and ranges properties for the reg property of all ITS nodes. diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index dfd908630631..081722240936 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -538,6 +538,14 @@ config QCOM_QDF2400_ERRATUM_0065 If unsure, say Y. +config SOCIONEXT_SYNQUACER_PREITS + bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" + default y + help + Socionext Synquacer SoCs implement a separate h/w block to generate + MSI doorbell writes with non-zero values for the device ID. + + If unsure, say Y. endmenu diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 284738add89b..fb86b15fa10d 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -45,6 +45,7 @@ #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) +#define ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS (1ULL << 3) #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) @@ -85,6 +86,10 @@ struct its_node { struct its_collection *collections; struct list_head its_device_list; u64 flags; +#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS + u64 pre_its_base; + u64 pre_its_size; +#endif u32 ite_size; u32 device_ids; int numa_node; @@ -654,6 +659,23 @@ static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, return IRQ_SET_MASK_OK_DONE; } +static u64 its_irq_get_msi_base(struct its_node *its) +{ +#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS + if (its->flags & ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS) + + /* + * The Socionext Synquacer SoC has a so-called 'pre-ITS', + * which maps 32-bit writes targeted at a separate window of + * size '4 << device_id_bits' onto writes to GITS_TRANSLATER + * with device ID taken from bits [device_id_bits + 1:2] of + * the window offset. + */ + return its->pre_its_base + (its_dev->device_id << 2); +#endif + return its->phys_base + GITS_TRANSLATER; +} + static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) { struct its_device *its_dev = irq_data_get_irq_chip_data(d); @@ -661,12 +683,15 @@ static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) u64 addr; its = its_dev->its; - addr = its->phys_base + GITS_TRANSLATER; + addr = its_irq_get_msi_base(its); msg->address_lo = lower_32_bits(addr); msg->address_hi = upper_32_bits(addr); msg->data = its_get_event_id(d); + if (its->flags & ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS) + return; + iommu_dma_map_msi_msg(d->irq, msg); } @@ -1044,6 +1069,11 @@ static int its_alloc_tables(struct its_node *its) ids = 0x14; /* 20 bits, 8MB */ } +#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS + if (its->flags & ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS) + ids = ilog2(its->pre_its_size) - 2; +#endif + its->device_ids = ids; for (i = 0; i < GITS_BASER_NR_REGS; i++) { @@ -1640,11 +1670,21 @@ static const struct gic_quirk its_quirks[] = { } }; -static void its_enable_quirks(struct its_node *its) +static void its_enable_quirks(struct its_node *its, + struct fwnode_handle *handle) { u32 iidr = readl_relaxed(its->base + GITS_IIDR); gic_enable_quirks(iidr, its_quirks, its); + +#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS + if (!fwnode_property_read_u64_array(handle, + "socionext,synquacer-pre-its", + &its->pre_its_base, 2)) { + its->flags |= ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS; + pr_info("ITS: enabling workaround for Socionext Synquacer pre-ITS\n"); + } +#endif } static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) @@ -1664,7 +1704,9 @@ static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) inner_domain->parent = its_parent; irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); - inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP; + + if (!(its->flags & ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS)) + inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP; info->ops = &its_msi_domain_ops; info->data = its; inner_domain->host_data = info; @@ -1724,7 +1766,7 @@ static int __init its_probe_one(struct resource *res, } its->cmd_write = its->cmd_base; - its_enable_quirks(its); + its_enable_quirks(its, handle); err = its_alloc_tables(its); if (err)