[01/10] site: Add riscv32 and riscv64

Message ID 79796969192ddd9bebbb7bc4647208443278154f.1507250774.git.raj.khem@gmail.com
State New
Headers show
Series
  • Add foundation for riscv architecture
Related show

Commit Message

Khem Raj Oct. 6, 2017, 12:50 a.m.
Signed-off-by: Khem Raj <raj.khem@gmail.com>

---
 meta/site/riscv32-linux | 4 ++++
 meta/site/riscv64-linux | 4 ++++
 2 files changed, 8 insertions(+)
 create mode 100644 meta/site/riscv32-linux
 create mode 100644 meta/site/riscv64-linux

-- 
2.14.2

-- 
_______________________________________________
Openembedded-core mailing list
Openembedded-core@lists.openembedded.org
http://lists.openembedded.org/mailman/listinfo/openembedded-core

Patch

diff --git a/meta/site/riscv32-linux b/meta/site/riscv32-linux
new file mode 100644
index 0000000000..a496bd1aca
--- /dev/null
+++ b/meta/site/riscv32-linux
@@ -0,0 +1,4 @@ 
+# glib-2.0
+glib_cv_stack_grows=${glib_cv_stack_grows=no}
+glib_cv_uscore=${glib_cv_uscore=no}
+
diff --git a/meta/site/riscv64-linux b/meta/site/riscv64-linux
new file mode 100644
index 0000000000..a496bd1aca
--- /dev/null
+++ b/meta/site/riscv64-linux
@@ -0,0 +1,4 @@ 
+# glib-2.0
+glib_cv_stack_grows=${glib_cv_stack_grows=no}
+glib_cv_uscore=${glib_cv_uscore=no}
+