From patchwork Thu Sep 20 09:46:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 11528 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 773FE23E41 for ; Thu, 20 Sep 2012 09:47:05 +0000 (UTC) Received: from mail-ie0-f180.google.com (mail-ie0-f180.google.com [209.85.223.180]) by fiordland.canonical.com (Postfix) with ESMTP id 81F0F3D09A00 for ; Thu, 20 Sep 2012 09:46:18 +0000 (UTC) Received: by mail-ie0-f180.google.com with SMTP id e10so2545757iej.11 for ; Thu, 20 Sep 2012 02:46:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:mime-version:content-type :x-gm-message-state; bh=ROlOpK3sLfV4oxgvGoix8Wgh5QfOUiTrRWk+MDKXoPc=; b=AD4RQQ+Cc1mlamOSRx5R00amgHDYcfa7T32v9smw3pjFCSt9JP5Xflkn10tn4EnDGj BHjP0c6GvqPXJDJmeqEpndKg0wZwmrQQYYHjC6VCA7T5jKkE9Z3Fahjvb+vKYg0z6gEy yK4S2CABDjfgD9iwoWPAVpHt9+qnj0Bkr88vSdjq5HADwtxUN5xM2c12SHUgas5Ovd+o MIg/BGQomquuCtF9Kek43u2ynEVvWzfvhTcFbpe3bhDMYjypNY0UcdLFmTmnON+j1Z0l s51KRVY6xIJaPqpF3AsG9yAofVbxeAKvaUWUeGjHGVW5GYy+7ALpkMnQubnopvq+ftWx kHRw== Received: by 10.42.84.69 with SMTP id k5mr1001979icl.5.1348134378304; Thu, 20 Sep 2012 02:46:18 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.50.184.232 with SMTP id ex8csp65943igc; Thu, 20 Sep 2012 02:46:17 -0700 (PDT) Received: by 10.14.201.73 with SMTP id a49mr976806eeo.39.1348134377226; Thu, 20 Sep 2012 02:46:17 -0700 (PDT) Received: from eu1sys200aog115.obsmtp.com (eu1sys200aog115.obsmtp.com [207.126.144.139]) by mx.google.com with SMTP id 43si3349565eei.53.2012.09.20.02.46.09 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 20 Sep 2012 02:46:17 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.139 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.139; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.139 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob115.postini.com ([207.126.147.11]) with SMTP ID DSNKUFrl4MIzCKr0AqmNDJvPW1eM8MDw7Xbo@postini.com; Thu, 20 Sep 2012 09:46:16 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 41FD097; Thu, 20 Sep 2012 09:37:50 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 7B991A76; Thu, 20 Sep 2012 09:46:04 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 5172724C2F7; Thu, 20 Sep 2012 11:45:58 +0200 (CEST) Received: from steludxu4075.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Thu, 20 Sep 2012 11:46:03 +0200 From: Linus Walleij To: , Greg Kroah-Hartman Cc: , Anmar Oueja , Linus Walleij , Bibek Basu , Par-Gunnar Hjalmdahl , Guillaume Jaunet , Christophe Arnal , Matthias Locher , Rajanikanth H.V Subject: [PATCH 2/3] serial: pl011: handle corruption at high clock speeds Date: Thu, 20 Sep 2012 11:46:00 +0200 Message-ID: <1348134360-25628-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.11.3 MIME-Version: 1.0 X-Gm-Message-State: ALoCoQn2DEOpzNMDttO1h/Z9HD/c1H1zrRIu7e6cn41WiiZWWCXxEK6LyfLtX1DIKpbRroDzt0vv From: Linus Walleij This works around a few glitches in the ST version of the PL011 serial driver when using very high baud rates, as we do in the Ux500: 3, 3.25, 4 and 4.05 Mbps are used in our platform. Problem Observed/rootcause: In case of high baud-rates, where the baud-rate*8 is getting close to the provided clock frequency (so a division factor close to 1) when using bursts of characters (so they are abutted), then it seems as if there is not enough time to detect the beginning of the start-bit which is a timing reference for the entire character, and thus the sampling moment of character bits is moving towards the end of each bit, instead of the middle. Fix: Increase slightly the RX baud rate of the UART above the theoretical baudrate by 5%. This will definitely give more margin time to the UART_RX to sample correctly the data at the middle of the bit period. Cc: Bibek Basu Cc: Par-Gunnar Hjalmdahl Signed-off-by: Guillaume Jaunet Signed-off-by: Christophe Arnal Signed-off-by: Matthias Locher Signed-off-by: Rajanikanth H.V Signed-off-by: Linus Walleij --- drivers/tty/serial/amba-pl011.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 9e16ea6..32240a7 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c @@ -1601,13 +1601,26 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios, old_cr &= ~ST_UART011_CR_OVSFACT; } + /* + * Workaround for the ST Micro oversampling variants to + * increase the bitrate slightly, by lowering the divisor, + * to avoid delayed sampling of start bit at high speeds, + * else we see data corruption. + */ + if (uap->vendor->oversampling) { + if (baud > 3000000 && baud < 3250000 && quot > 1) + quot -= 1; + else if (baud > 3250000 && quot > 2) + quot -= 2; + } /* Set baud rate */ writew(quot & 0x3f, port->membase + UART011_FBRD); writew(quot >> 6, port->membase + UART011_IBRD); /* * ----------v----------v----------v----------v----- - * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L + * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER + * UARTLCR_M(IBRD) & UARTLCR_L(FBRD). * ----------^----------^----------^----------^----- */ writew(lcr_h, port->membase + uap->lcrh_rx);