From patchwork Thu Oct 12 06:58:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 115592 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp1604667qgn; Wed, 11 Oct 2017 23:58:59 -0700 (PDT) X-Received: by 10.98.214.17 with SMTP id r17mr1389482pfg.246.1507791539486; Wed, 11 Oct 2017 23:58:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507791539; cv=none; d=google.com; s=arc-20160816; b=M+H4wAyXWjZxJ9CI1jPZBc729CCrko7femNNCcg9/2TyArHrZeKqkWCxOgRgPf/e20 CNfGZ8DLjJyFTYpPbMPMP5xmvc03WS1r6vSxdROnSsMoS+yC+tivH4vLMCGjvbJpQn6d 5uTWCAdonL7kOxYeV+awD2rSqEEoWwbhdLxLpkjQc2ySTAADKqRQBjng6XS5Ojcy2GBb a0GgDTax830mrP3W1XftOc5CSZI5vXtoB7LmLGtRfGqGizLCu/zm2y0xlDwoFl3NUCwY jh98daeinAFWOdDa+C1LuUY5dvN3nh4s6avuPE1VLQgtImSX6NRNKTGd9S3mA2RxieGj noJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=xh82CHZ6k5g5VALv09TAyB8rDbdv93G+GoofGHOsFeY=; b=SCIwAfg8hgGVTQocwULb3YCVR3U+2sQmgaYTg2SFgDnZOL7GzxjklvgxfyTR/a4Zgx 79OCI/OoBUpQXyRLizK3dgl1YdiiqX26rfEUDlG/AhBJGHXHaizDf0jIA5ali0uPQKa1 +5VlGsvqBkKZNX/bkLCniG3IxbvjglGfRR1oCElsI14k4gzyudTbG/gmrDQrfK8Lqe3O 9wnOCWkCDqrmKODqT9i9AwK3+0+p+7oFUvY7iiuh2oWd4EsWOYvC13rtrYLx1xoM71ja xRh6QxdjTqniQGlMtKTm9lpT52lwvr88JtPJdx1XPKzk6ZTkcSQnDRKVxlpfqxS66fFC g5ZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Hg0yuSVB; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q66si10946127pga.462.2017.10.11.23.58.59; Wed, 11 Oct 2017 23:58:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Hg0yuSVB; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752501AbdJLG66 (ORCPT + 6 others); Thu, 12 Oct 2017 02:58:58 -0400 Received: from mail-wm0-f50.google.com ([74.125.82.50]:49020 "EHLO mail-wm0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752175AbdJLG65 (ORCPT ); Thu, 12 Oct 2017 02:58:57 -0400 Received: by mail-wm0-f50.google.com with SMTP id i124so10186991wmf.3 for ; Wed, 11 Oct 2017 23:58:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=WOIx6Vg9c4FCRDF+S/+h7wZiEp8DcqmO5aDJIZoFRSQ=; b=Hg0yuSVBxbLRHZLZ9isJccqEr/tYbS3lVc1jtUmAzMNET5E1ZqJR/n/HUfeY3JxcWZ gVcDahN68TDHoBa+v0DONNQ/VsnornMCE4anLpTVHnlI8gymyPetRvS7tvt5cfTnPjFU Nsvw1UuScOczCBnqiUGHnrnl8V//bALV1+Kts= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=WOIx6Vg9c4FCRDF+S/+h7wZiEp8DcqmO5aDJIZoFRSQ=; b=k5LveYtfbrX8VxO5npw/qZ0HCDzT3dBU3U2HRyZQIieYwsGmWLdX9TmKaS8ucxhADg LQYp1QlPAhwuUTdykpsjIxWkdI4FqDMJ6ZdcpL4B5dyazC0wV4fSY6HsOxfA81pZl3q+ KozD98CnhSZONLsvpuwLLTmh/D5bxq30OAJj6O7PfRQtOLCwJkIZ06ntuWMf/XWN28Vc 3BsgHmBfFpgnhPU+W4aNHIWzRWQkMWvm61dW/acm7bJ2pZLWlbqj1mokgG6vbA7zce3S rqoIyFsmChQNhJyAHUGvbl8gKDMXLKDaBKuWwbbQpo9Es80aixt1kFDjvrxqkkzbnkRO WdeA== X-Gm-Message-State: AMCzsaWyhpP/+WStv0r0EPpS80qZRVcleyJ0WErR1tP2Ty0S3/7dz0li 4nZHcvgx5eeYrdHjC1wUXYuvUg== X-Google-Smtp-Source: AOwi7QCy16ocI1G9KPD82fAvuYRpc9BUY7dORnL7GO7n8yLV2mLuNAHHSgolPqo9l47khxyjXBE6xA== X-Received: by 10.223.184.15 with SMTP id h15mr1274032wrf.123.1507791536295; Wed, 11 Oct 2017 23:58:56 -0700 (PDT) Received: from localhost.localdomain ([196.78.24.219]) by smtp.gmail.com with ESMTPSA id b190sm18932713wma.41.2017.10.11.23.58.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Oct 2017 23:58:55 -0700 (PDT) From: Ard Biesheuvel To: marc.zyngier@arm.com, robin.murphy@arm.com Cc: linux-arm-kernel@lists.infradead.org, daniel.thompson@Linaro.org, leif.lindholm@linaro.org, graeme.gregory@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, Ard Biesheuvel Subject: [PATCH v2] drivers/irqchip: gicv3: add workaround for Synquacer pre-ITS Date: Thu, 12 Oct 2017 07:58:35 +0100 Message-Id: <20171012065835.646-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Socionext Synquacer SoC's implementation of GICv3 has a so-called 'pre-ITS', which maps 32-bit writes targeted at a separate window of size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device ID taken from bits [device_id_bits + 1:2] of the window offset. Writes that target GITS_TRANSLATER directly are reported as originating from device ID #0. So add a workaround for this. Given that this breaks isolation, clear the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well. Signed-off-by: Ard Biesheuvel --- v2: - use a 32-bit host address/size rather than a PCI address, to factor out the involvement of an SMMU (which the platform does have, but it is unclear atm if it can be exposed to the OS) - add msi_domain_flags member to move the quirk flag checks out of the common code path Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 4 ++ arch/arm64/Kconfig | 8 +++ drivers/irqchip/irq-gic-v3-its.c | 53 +++++++++++++++++--- 3 files changed, 59 insertions(+), 6 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index 4c29cdab0ea5..3d8b3f910aef 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -75,6 +75,10 @@ These nodes must have the following properties: - reg: Specifies the base physical address and size of the ITS registers. +Optional: +- socionext,synquacer-pre-its: (u32, u32) tuple describing the host address + and size of the pre-ITS window. + The main GIC node must contain the appropriate #address-cells, #size-cells and ranges properties for the reg property of all ITS nodes. diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0df64a6a56d4..c4361dff2b74 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -539,6 +539,14 @@ config QCOM_QDF2400_ERRATUM_0065 If unsure, say Y. +config SOCIONEXT_SYNQUACER_PREITS + bool "Socionext Synquacer: Workaround for GICv3 pre-ITS" + default y + help + Socionext Synquacer SoCs implement a separate h/w block to generate + MSI doorbell writes with non-zero values for the device ID. + + If unsure, say Y. endmenu diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index e8d89343d613..7a4536ce8e72 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -46,6 +46,7 @@ #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) #define ITS_FLAGS_WORKAROUND_CAVIUM_22375 (1ULL << 1) #define ITS_FLAGS_WORKAROUND_CAVIUM_23144 (1ULL << 2) +#define ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS (1ULL << 3) #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0) @@ -102,6 +103,11 @@ struct its_node { u32 ite_size; u32 device_ids; int numa_node; + unsigned int msi_domain_flags; +#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS + u32 pre_its_base; + u32 pre_its_size; +#endif bool is_v4; }; @@ -1095,14 +1101,31 @@ static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val, return IRQ_SET_MASK_OK_DONE; } +static u64 its_irq_get_msi_base(struct its_device *its_dev) +{ + struct its_node *its = its_dev->its; + +#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS + if (its->flags & ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS) + + /* + * The Socionext Synquacer SoC has a so-called 'pre-ITS', + * which maps 32-bit writes targeted at a separate window of + * size '4 << device_id_bits' onto writes to GITS_TRANSLATER + * with device ID taken from bits [device_id_bits + 1:2] of + * the window offset. + */ + return its->pre_its_base + (its_dev->device_id << 2); +#endif + return its->phys_base + GITS_TRANSLATER; +} + static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg) { struct its_device *its_dev = irq_data_get_irq_chip_data(d); - struct its_node *its; u64 addr; - its = its_dev->its; - addr = its->phys_base + GITS_TRANSLATER; + addr = its_irq_get_msi_base(its_dev); msg->address_lo = lower_32_bits(addr); msg->address_hi = upper_32_bits(addr); @@ -1666,6 +1689,11 @@ static int its_alloc_tables(struct its_node *its) ids = 0x14; /* 20 bits, 8MB */ } +#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS + if (its->flags & ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS) + ids = ilog2(its->pre_its_size) - 2; +#endif + its->device_ids = ids; for (i = 0; i < GITS_BASER_NR_REGS; i++) { @@ -2788,11 +2816,22 @@ static const struct gic_quirk its_quirks[] = { } }; -static void its_enable_quirks(struct its_node *its) +static void its_enable_quirks(struct its_node *its, + struct fwnode_handle *handle) { u32 iidr = readl_relaxed(its->base + GITS_IIDR); gic_enable_quirks(iidr, its_quirks, its); + +#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS + if (!fwnode_property_read_u32_array(handle, + "socionext,synquacer-pre-its", + &its->pre_its_base, 2)) { + its->flags |= ITS_FLAGS_WORKAROUND_SOCIONEXT_PREITS; + its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP; + pr_info("ITS: enabling workaround for Socionext Synquacer pre-ITS\n"); + } +#endif } static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) @@ -2811,8 +2850,9 @@ static int its_init_domain(struct fwnode_handle *handle, struct its_node *its) } inner_domain->parent = its_parent; + inner_domain->flags |= its->msi_domain_flags; irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS); - inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_REMAP; + info->ops = &its_msi_domain_ops; info->data = its; inner_domain->host_data = info; @@ -2942,6 +2982,7 @@ static int __init its_probe_one(struct resource *res, its->base = its_base; its->phys_base = res->start; its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer); + its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP; its->is_v4 = !!(typer & GITS_TYPER_VLPIS); if (its->is_v4) { if (!(typer & GITS_TYPER_VMOVP)) { @@ -2966,7 +3007,7 @@ static int __init its_probe_one(struct resource *res, } its->cmd_write = its->cmd_base; - its_enable_quirks(its); + its_enable_quirks(its, handle); err = its_alloc_tables(its); if (err)