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[PULL,07/13] target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1

Message ID 1507824216-29058-8-git-send-email-peter.maydell@linaro.org
State Accepted
Commit 6b8acf256df09c8a8dd7dcaa79b06eaff4ad63f7
Headers show
Series target-arm queue | expand

Commit Message

Peter Maydell Oct. 12, 2017, 4:03 p.m. UTC 
The code which implements the Thumb1 split BL/BLX instructions
is guarded by a check on "not M or THUMB2". All we really need
to check here is "not THUMB2" (and we assume that elsewhere too,
eg in the ARCH(6T2) test that UNDEFs the Thumb2 insns).

This doesn't change behaviour because all M profile cores
have Thumb2 and so ARM_FEATURE_M implies ARM_FEATURE_THUMB2.
(v6M implements a very restricted subset of Thumb2, but we
can cross that bridge when we get to it with appropriate
feature bits.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 1507556919-24992-6-git-send-email-peter.maydell@linaro.org
---
 target/arm/translate.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

-- 
2.7.4
diff mbox series

Patch

diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5c6f9fe..530a5c4 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9719,8 +9719,7 @@  static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
     int conds;
     int logic_cc;
 
-    if (!(arm_dc_feature(s, ARM_FEATURE_THUMB2)
-          || arm_dc_feature(s, ARM_FEATURE_M))) {
+    if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) {
         /* Thumb-1 cores may need to treat bl and blx as a pair of
            16-bit instructions to get correct prefetch abort behavior.  */
         insn = insn_hw1;