From patchwork Fri Oct 13 10:22:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 115739 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp565383qgn; Fri, 13 Oct 2017 03:33:30 -0700 (PDT) X-Google-Smtp-Source: AOwi7QBsXioVXHK68RLcLO5E27Evkauh/WaBQyNMPyPF0NzDqdIoi7oBdx+jGkkDz7ni70DsMZAs X-Received: by 10.80.166.133 with SMTP id e5mr1508258edc.51.1507890810833; Fri, 13 Oct 2017 03:33:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1507890810; cv=none; d=google.com; s=arc-20160816; b=K2lvwRlFVT359I8Ck33FKliMB7bZ5GAYbwhuEGAkVpeSncMELDLXVoUrxv7TxK87VL 6EyHQraGP7pYoPlrW/NkWkqmH6MA2WrPvYNtQdaC3f1EuN6As9L108PL0gtK3bLuYaNR 5s2z2Cbgz+lNbitpsanPMC3HYLPamTJeAxeDN2Eq676neiAOO1/vJb8qHNghANPbsdox vv19qfcmogU6gz5spROZlNSZTbtwR0eV7hLy24x3vEHrA8KliE/PiCJ2pmbubHobWTu5 5p49McwxBnmBhhKAbmmuoFdl51qtcsfqnEAZdh4q3GEOc2H/1L7kbA/qJP/Cqyjv17X9 YD+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:references:in-reply-to:message-id:date :to:from:dkim-signature:dkim-filter:arc-authentication-results; bh=/LWMp0vQ1pHIRdHWFzr97fUFrxqcMUja4sTAfsBe3wI=; b=beoCvNW0jNILyZmwGbv5ehB7Fdl4Cuxw5YJ6Lm1PdBonazb7UlRng9sAFGlINkzxcN Zs4N1AXzEWbM+1/5ohaQBOQwEgK8fUN8xqxJIk+hqXPL1h9F1f0BDoqIC+4tS0vFF1LN FNyIsaP0I4kTEDvcLnpjZaKs6yssHWAVnCDRIkCkWW/LN2KXr9gMosNCK0Zab1HVGP3q Ok5eGsNRwIXiTBT95osNjupY/TceMKnFKhkuQhMSV0tvQvf1tw1zyxynRY7bWq8Nltet GLilDwiuwocM3yjPlXhfxOYOPax6Vz4Z3skr97eq3ynERgyD8wQ7Bo7ljAk5vM9nWuLe 3d2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=EzH0AqCl; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id c5si193762edl.342.2017.10.13.03.33.30; Fri, 13 Oct 2017 03:33:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com header.s=dec2015msa header.b=EzH0AqCl; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by lists.denx.de (Postfix, from userid 105) id 72441C21E6F; Fri, 13 Oct 2017 10:26:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3EF97C21FDA; Fri, 13 Oct 2017 10:22:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 56704C21D99; Fri, 13 Oct 2017 10:22:40 +0000 (UTC) Received: from conuserg-12.nifty.com (conuserg-12.nifty.com [210.131.2.79]) by lists.denx.de (Postfix) with ESMTPS id 9AEDAC21EF3 for ; Fri, 13 Oct 2017 10:22:39 +0000 (UTC) Received: from pug.e01.socionext.com (p14092-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.92]) (authenticated) by conuserg-12.nifty.com with ESMTP id v9DAMGxF009903; Fri, 13 Oct 2017 19:22:23 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-12.nifty.com v9DAMGxF009903 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1507890143; bh=axRav+jD1fKL57FvwUgzKQLV9SzPIPGie/f8+w5y50o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EzH0AqClh1BiGs0OUL7ykJ1LOSIH/Vll86d2T+R/2pRUGwBEY9ygX+Ub0wZPAtsV8 uUADR0n0mbU4aEMnhhRIf6kjo0GwlrR8BXLcdAil+XZYwryW87K4E7k5N1VWUBvxWS INnL8RRNNqES+0E/9arFq4eo6H3pi0h+6VQWrTEJ9MWwqN6uIdrqJE3ifGzWnMnFRn WkLb2uZQCjV7HOXzpxsQu/VY3rWNDRWAC8kxsMwhQV65Nfg7tMZyAzUcHMKAgye6Tm BxhHwTYSIzVg7ZiVBaYTbx0qTAqSn1/VCCrRAOfhIkOAvfYyVwQW4P4qadSXdx5SYL Sp/kJwpzNKzXQ== X-Nifty-SrcIP: [153.142.97.92] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Fri, 13 Oct 2017 19:22:01 +0900 Message-Id: <1507890129-1543-13-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1507890129-1543-1-git-send-email-yamada.masahiro@socionext.com> References: <1507890129-1543-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 12/20] clk: uniphier: add peripheral clock data X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add peripheral clock data for all SoCs. Signed-off-by: Masahiro Yamada --- drivers/clk/uniphier/Makefile | 2 + drivers/clk/uniphier/clk-uniphier-core.c | 33 +++++++++ drivers/clk/uniphier/clk-uniphier-peri.c | 113 +++++++++++++++++++++++++++++++ drivers/clk/uniphier/clk-uniphier.h | 5 ++ 4 files changed, 153 insertions(+) create mode 100644 drivers/clk/uniphier/clk-uniphier-peri.c diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile index 54c7e09..d132cf7 100644 --- a/drivers/clk/uniphier/Makefile +++ b/drivers/clk/uniphier/Makefile @@ -1,3 +1,5 @@ obj-y += clk-uniphier-core.o + obj-y += clk-uniphier-sys.o obj-y += clk-uniphier-mio.o +obj-y += clk-uniphier-peri.o diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 9a7d03a..ed5acbd 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -333,6 +333,39 @@ static const struct udevice_id uniphier_clk_match[] = { .compatible = "socionext,uniphier-pxs3-sd-clock", .data = (ulong)uniphier_mio_clk_data, }, + /* Peripheral clock */ + { + .compatible = "socionext,uniphier-ld4-peri-clock", + .data = (ulong)uniphier_ld4_peri_clk_data, + }, + { + .compatible = "socionext,uniphier-pro4-peri-clock", + .data = (ulong)uniphier_pro4_peri_clk_data, + }, + { + .compatible = "socionext,uniphier-sld8-peri-clock", + .data = (ulong)uniphier_sld8_peri_clk_data, + }, + { + .compatible = "socionext,uniphier-pro5-peri-clock", + .data = (ulong)uniphier_pro4_peri_clk_data, + }, + { + .compatible = "socionext,uniphier-pxs2-peri-clock", + .data = (ulong)uniphier_pxs2_peri_clk_data, + }, + { + .compatible = "socionext,uniphier-ld11-peri-clock", + .data = (ulong)uniphier_ld11_peri_clk_data, + }, + { + .compatible = "socionext,uniphier-ld20-peri-clock", + .data = (ulong)uniphier_ld11_peri_clk_data, + }, + { + .compatible = "socionext,uniphier-pxs3-peri-clock", + .data = (ulong)uniphier_ld11_peri_clk_data, + }, { /* sentinel */ } }; diff --git a/drivers/clk/uniphier/clk-uniphier-peri.c b/drivers/clk/uniphier/clk-uniphier-peri.c new file mode 100644 index 0000000..51edcab --- /dev/null +++ b/drivers/clk/uniphier/clk-uniphier-peri.c @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2016-2017 Socionext Inc. + * Author: Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "clk-uniphier.h" + +#define UNIPHIER_PERI_CLK_UART(id, ch) \ + UNIPHIER_CLK_GATE(id, 128, 0x24, 19 + (ch)) + +#define UNIPHIER_PERI_CLK_I2C(id, ch) \ + UNIPHIER_CLK_GATE(id, 129, 0x24, 5 + (ch)) + +#define UNIPHIER_PERI_CLK_FI2C(id, ch) \ + UNIPHIER_CLK_GATE(id, 129, 0x24, 24 + (ch)) + +const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = { +#ifdef CONFIG_ARCH_UNIPHIER_LD4 + UNIPHIER_CLK_RATE(128, 36864000), + UNIPHIER_CLK_RATE(129, 99840000), + UNIPHIER_PERI_CLK_UART(0, 0), + UNIPHIER_PERI_CLK_UART(1, 1), + UNIPHIER_PERI_CLK_UART(2, 2), + UNIPHIER_PERI_CLK_UART(3, 3), + UNIPHIER_PERI_CLK_I2C(4, 0), + UNIPHIER_PERI_CLK_I2C(5, 1), + UNIPHIER_PERI_CLK_I2C(6, 2), + UNIPHIER_PERI_CLK_I2C(7, 3), + UNIPHIER_PERI_CLK_I2C(8, 4), + UNIPHIER_PERI_CLK_I2C(9, 5), + UNIPHIER_PERI_CLK_I2C(10, 6), + { /* sentinel */ } +#endif +}; + +const struct uniphier_clk_data uniphier_sld8_peri_clk_data[] = { +#ifdef CONFIG_ARCH_UNIPHIER_SLD8 + UNIPHIER_CLK_RATE(128, 80000000), + UNIPHIER_CLK_RATE(129, 100000000), + UNIPHIER_PERI_CLK_UART(0, 0), + UNIPHIER_PERI_CLK_UART(1, 1), + UNIPHIER_PERI_CLK_UART(2, 2), + UNIPHIER_PERI_CLK_UART(3, 3), + UNIPHIER_PERI_CLK_I2C(4, 0), + UNIPHIER_PERI_CLK_I2C(5, 1), + UNIPHIER_PERI_CLK_I2C(6, 2), + UNIPHIER_PERI_CLK_I2C(7, 3), + UNIPHIER_PERI_CLK_I2C(8, 4), + UNIPHIER_PERI_CLK_I2C(9, 5), + UNIPHIER_PERI_CLK_I2C(10, 6), + { /* sentinel */ } +#endif +}; + +const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = { +#if defined(CONFIG_ARCH_UNIPHIER_PRO4) || defined(CONFIG_ARCH_UNIPHIER_PRO5) + UNIPHIER_CLK_RATE(128, 73728000), + UNIPHIER_CLK_RATE(129, 50000000), + UNIPHIER_PERI_CLK_UART(0, 0), + UNIPHIER_PERI_CLK_UART(1, 1), + UNIPHIER_PERI_CLK_UART(2, 2), + UNIPHIER_PERI_CLK_UART(3, 3), + UNIPHIER_PERI_CLK_FI2C(4, 0), + UNIPHIER_PERI_CLK_FI2C(5, 1), + UNIPHIER_PERI_CLK_FI2C(6, 2), + UNIPHIER_PERI_CLK_FI2C(7, 3), + UNIPHIER_PERI_CLK_FI2C(8, 4), + UNIPHIER_PERI_CLK_FI2C(9, 5), + UNIPHIER_PERI_CLK_FI2C(10, 6), + { /* sentinel */ } +#endif +}; + +const struct uniphier_clk_data uniphier_pxs2_peri_clk_data[] = { +#if defined(CONFIG_ARCH_UNIPHIER_PXS2) || defined(CONFIG_ARCH_UNIPHIER_LD6B) + UNIPHIER_CLK_RATE(128, 88888889), + UNIPHIER_CLK_RATE(129, 50000000), + UNIPHIER_PERI_CLK_UART(0, 0), + UNIPHIER_PERI_CLK_UART(1, 1), + UNIPHIER_PERI_CLK_UART(2, 2), + UNIPHIER_PERI_CLK_UART(3, 3), + UNIPHIER_PERI_CLK_FI2C(4, 0), + UNIPHIER_PERI_CLK_FI2C(5, 1), + UNIPHIER_PERI_CLK_FI2C(6, 2), + UNIPHIER_PERI_CLK_FI2C(7, 3), + UNIPHIER_PERI_CLK_FI2C(8, 4), + UNIPHIER_PERI_CLK_FI2C(9, 5), + UNIPHIER_PERI_CLK_FI2C(10, 6), + { /* sentinel */ } +#endif +}; + +const struct uniphier_clk_data uniphier_ld11_peri_clk_data[] = { +#if defined(CONFIG_ARCH_UNIPHIER_LD11) || defined(CONFIG_ARCH_UNIPHIER_LD20) ||\ + defined(CONFIG_ARCH_UNIPHIER_PXS3) + UNIPHIER_CLK_RATE(128, 58823529), + UNIPHIER_CLK_RATE(129, 50000000), + UNIPHIER_PERI_CLK_UART(0, 0), + UNIPHIER_PERI_CLK_UART(1, 1), + UNIPHIER_PERI_CLK_UART(2, 2), + UNIPHIER_PERI_CLK_UART(3, 3), + UNIPHIER_PERI_CLK_FI2C(4, 0), + UNIPHIER_PERI_CLK_FI2C(5, 1), + UNIPHIER_PERI_CLK_FI2C(6, 2), + UNIPHIER_PERI_CLK_FI2C(7, 3), + UNIPHIER_PERI_CLK_FI2C(8, 4), + UNIPHIER_PERI_CLK_FI2C(9, 5), + UNIPHIER_PERI_CLK_FI2C(10, 6), + { /* sentinel */ } +#endif +}; diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h index 77ebae1..5706db5 100644 --- a/drivers/clk/uniphier/clk-uniphier.h +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -75,5 +75,10 @@ extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_pxs3_sys_clk_data[]; extern const struct uniphier_clk_data uniphier_mio_clk_data[]; +extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[]; +extern const struct uniphier_clk_data uniphier_sld8_peri_clk_data[]; +extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[]; +extern const struct uniphier_clk_data uniphier_pxs2_peri_clk_data[]; +extern const struct uniphier_clk_data uniphier_ld11_peri_clk_data[]; #endif /* __CLK_UNIPHIER_H__ */