From patchwork Wed Oct 18 11:00:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiancheng Xue X-Patchwork-Id: 116175 Delivered-To: patch@linaro.org Received: by 10.140.22.163 with SMTP id 32csp5582871qgn; Tue, 17 Oct 2017 19:57:58 -0700 (PDT) X-Google-Smtp-Source: ABhQp+Qpr4hyraUEPKpRhvsRMJJhj9Tm2ncm3SK5rZLaOQ/2jFQvKW6JY7L6Q4iR1KDw25kNRsLq X-Received: by 10.84.138.193 with SMTP id 59mr5099488plp.446.1508295478632; Tue, 17 Oct 2017 19:57:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508295478; cv=none; d=google.com; s=arc-20160816; b=SAFZsqUxXro6VqMOxLjmcH7eZ10bve8QMp7gk6hd/CZ7VRpMTjqET+pYmyZwL6umhs Hn5CokKy2sVhumuV7pzHW5bJbwLQBpGuNa4LRx9POA/f/mLgZYiLHoWihbXg5hDw6e8O fOimJ8EW4jaR42aSbQqj26gVJhMGj/Z7b31irdKoWRf0X7oxUgFMY++dSo5O4ziGIgc9 sTXlAHalaNfC7AGz3lTYgtssD3PUetRdXwhCkjo/XC+Qx+WVuZUlBSFtUIBzqDAAnEku 7A84BqG1kkYA/XuyP5E3qW2AqRAiuqp2nR8zNj7ARr2A1Nkc1Nekr1rn71GJWJ9QUCvm 7i6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=028Af3izphpJwPFvgXFUTXceMQfpCfKMGCR4UXMoQHI=; b=mN/I2IGbt04P0JPd5pZRgWIP2ewyuRQbatZQzA4vsg7G9Rgu1xO1hcW1gDTNxr55rv LAVJJPsFTZ4KclA1IZ2msTzIv/FPmwp1nBTH3id/+XclaDrGc0rdwQMMoiNkHOtzzQt/ nzbfMc15T6L1c5ziBDf7FRSimMhiFUF4P6kpuC8x6y5D17C66oLhZnsEm6qXkyltpgm0 DKCwuIMLbL0sT89LHr0Mdqm5nlaDgotea1dvxwS3WBiifPyl/Bz9rhdqqmdscTEB2lwo pR5HYqSAd3dIbLAos3X2Q3eKMykbj+VTElaEdTCf80vQBUTRatz64PwY+mR94TxHXIIZ ngdA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f4si577180plm.686.2017.10.17.19.57.58; Tue, 17 Oct 2017 19:57:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757636AbdJRC5n (ORCPT + 27 others); Tue, 17 Oct 2017 22:57:43 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:8931 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757541AbdJRC5j (ORCPT ); Tue, 17 Oct 2017 22:57:39 -0400 Received: from 172.30.72.60 (EHLO DGGEMS413-HUB.china.huawei.com) ([172.30.72.60]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJG66698; Wed, 18 Oct 2017 10:57:24 +0800 (CST) Received: from arch-ubuntu.huawei.com (10.69.192.66) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.301.0; Wed, 18 Oct 2017 10:56:03 +0800 From: Jiancheng Xue To: , CC: , , , , , Younian Wang Subject: [PATCH 3/3] clk: hisilicon: correct ir clock rate for hi3798cv200 SoC Date: Wed, 18 Oct 2017 07:00:29 -0400 Message-ID: <1508324429-6012-4-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508324429-6012-1-git-send-email-xuejiancheng@hisilicon.com> References: <1508324429-6012-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.66] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090206.59E6C315.0041, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: bcd34a9fcbf4c08560e01e6b678d4b6e Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Younian Wang Correct ir clock rate for hi3798cv200 SoC. Signed-off-by: Younian Wang --- drivers/clk/hisilicon/crg-hi3798cv200.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4 diff --git a/drivers/clk/hisilicon/crg-hi3798cv200.c b/drivers/clk/hisilicon/crg-hi3798cv200.c index 25d750c..61bd941 100644 --- a/drivers/clk/hisilicon/crg-hi3798cv200.c +++ b/drivers/clk/hisilicon/crg-hi3798cv200.c @@ -258,7 +258,7 @@ static const struct hisi_crg_funcs hi3798cv200_crg_funcs = { #define HI3798CV200_SYSCTRL_NR_CLKS 16 static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = { - { HISTB_IR_CLK, "clk_ir", "100m", + { HISTB_IR_CLK, "clk_ir", "24m", CLK_SET_RATE_PARENT, 0x48, 4, 0, }, { HISTB_TIMER01_CLK, "clk_timer01", "24m", CLK_SET_RATE_PARENT, 0x48, 6, 0, },