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[209.132.180.67]) by mx.google.com with ESMTP id d19si6247560pgn.805.2017.10.17.20.13.55; Tue, 17 Oct 2017 20:13:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933368AbdJRDNw (ORCPT + 27 others); Tue, 17 Oct 2017 23:13:52 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:8519 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758804AbdJRDNs (ORCPT ); Tue, 17 Oct 2017 23:13:48 -0400 Received: from 172.30.72.59 (EHLO DGGEMS414-HUB.china.huawei.com) ([172.30.72.59]) by dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DJI63922; Wed, 18 Oct 2017 11:13:43 +0800 (CST) Received: from arch-ubuntu.huawei.com (10.69.192.66) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.301.0; Wed, 18 Oct 2017 11:11:48 +0800 From: Jiancheng Xue To: , , CC: , , , , , , , tianshuliang Subject: [PATCH 1/2] dt-bindings: mmc: add bindings for hi3798cv200-dw-mshc Date: Wed, 18 Oct 2017 07:16:27 -0400 Message-ID: <1508325388-7260-2-git-send-email-xuejiancheng@hisilicon.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508325388-7260-1-git-send-email-xuejiancheng@hisilicon.com> References: <1508325388-7260-1-git-send-email-xuejiancheng@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.66] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090204.59E6C6E7.006A, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 2ceb3179aa28614fcaf86543b291ed8f Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: tianshuliang Hisilicon hi3798cv200 SoC extends the dw-mshc controller for additional clock control. Add device tree bindings for hi3798cv200-dw-mshc. Signed-off-by: tianshuliang Signed-off-by: Jiancheng Xue --- .../bindings/mmc/hi3798cv200-dw-mshc.txt | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt -- 2.7.4 diff --git a/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt new file mode 100644 index 0000000..845c32c --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/hi3798cv200-dw-mshc.txt @@ -0,0 +1,51 @@ +* Hisilicon specific extensions to the Synopsys Designware Mobile + Storage Host Controller + +Read synopsys-dw-mshc.txt for more details + +The Synopsys designware mobile storage host controller is used to interface +a SoC with storage medium such as eMMC or SD/MMC cards. This file documents +differences between the core Synopsys dw mshc controller properties described +by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific +extensions to the Synopsys Designware Mobile Storage Host Controller. + +Required Properties: + +* compatible: should be one of the following. + - "hisilicon,hi3798cv200-dw-mshc": for controllers with hi3798cv200 specific extensions. + +Optional Properties: +* clocks: from common clock binding: if ciu-drive and ciu-sample are + specified in clock-names, should contain handles to these clocks. + +* clock-names:Apart from the clock-names described in synopsys-dw-mshc.txt + two more clocks "ciu-drive" and "ciu-sample" are supported. They are used + to control the clock phases, "ciu-sample" is required for tuning high-speed modes. + +Example: + + /* for Hi3798cv200 */ + + /* SoC portion */ + emmc: mmc@9830000 { + compatible = "hisilicon,hi3798cv200-dw-mshc"; + reg = <0x9830000 0x10000>; + interrupts = ; + clocks = <&crg HISTB_MMC_CIU_CLK>, + <&crg HISTB_MMC_BIU_CLK>, + <&crg HISTB_MMC_SAMPLE_CLK>; + clock-names = "ciu", "biu", "ciu-sample"; + }; + + /* Board portion */ + &emmc { + status = "okay"; + num-slots = <1>; + fifo-depth = <256>; + clock-frequency = <200000000>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + bus-width = <8>; + };