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[209.132.180.67]) by mx.google.com with ESMTP id m8si6966336pfh.552.2017.10.18.00.44.04; Wed, 18 Oct 2017 00:44:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=hAcVBqNx; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S935674AbdJRHn7 (ORCPT + 6 others); Wed, 18 Oct 2017 03:43:59 -0400 Received: from mail-wr0-f175.google.com ([209.85.128.175]:48897 "EHLO mail-wr0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S935673AbdJRHn6 (ORCPT ); Wed, 18 Oct 2017 03:43:58 -0400 Received: by mail-wr0-f175.google.com with SMTP id u5so4014096wrc.5 for ; Wed, 18 Oct 2017 00:43:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YRMDrn0GKD9HNuTlCPy7fMgZ2opjSCTXVxBYgWeWkDc=; b=hAcVBqNxXaVllW8HUDXkujDywdKp7cEBD1F5TgnIiwrN7p6at1W2VaBhUdQJusjXgu Ar0XRc349/kmKx4b3nyVBPh7/vZv0nlpacGbcyGEwSkJTHFVtMqe6FCv6Dvtn28bDlSn F4lXdPvlpZ8aOnCJPuGpFxeXQb9ZaBLHYCeZo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=YRMDrn0GKD9HNuTlCPy7fMgZ2opjSCTXVxBYgWeWkDc=; b=LR1E8i1D/Ipum3/mx9KUZatkuXopNE44dk6A4isEWy5GSh4DKud6ed7ms7ZifBnfZF nCRUdBffcaa4eQJI2rWWGsTNq8/cGtABtsIels6P5q9YhDie6GPXOYwusARZW97207FE 9Kuq5bSif4pMIOlVnRCS5nras0VsoSBF3w3Hq44yKYuozsNIwjCYo/72A6VWdjGO1U7Z WVxUNgutMweJ1fyH2E83uVqvtoVhZ+XAtg9o4oLlBExvCGLNllbONJ0iPw/VQdrPmYJp 6r3sYE5KuMzqFtFatV0gbbt2SakpFfRfrYLtbrROyo1HxhpZpz2T+aANcII3T+d6vn2c 2q2g== X-Gm-Message-State: AMCzsaVGgLYu2zvOUV1IU+Sqi5OYSL292RPwcmJ8mvIjwRIp0lapv7Se qS85ruGELHHweTneYI8YD6vH+Q== X-Google-Smtp-Source: ABhQp+TiVw9RF8sdswU+egKqZQhT1Su8A5GLxRiKOuzgdbDmz9C18qdZZp/4+nyesTbytdZKfkFzYw== X-Received: by 10.223.138.231 with SMTP id z36mr6167387wrz.154.1508312636830; Wed, 18 Oct 2017 00:43:56 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.215.78.118]) by smtp.gmail.com with ESMTPSA id v78sm7855063wmv.48.2017.10.18.00.43.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 18 Oct 2017 00:43:56 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v5 2/4] clocksource: stm32: only use 32 bits timers Date: Wed, 18 Oct 2017 09:43:32 +0200 Message-Id: <1508312614-27750-3-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508312614-27750-1-git-send-email-benjamin.gaignard@linaro.org> References: <1508312614-27750-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 16 bits hardware are not enough accure to be used. Do no allow them to be probed by tested max counter value. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index abff21c..f7e4eec 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -81,9 +81,9 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id) static int __init stm32_clockevent_init(struct device_node *node) { struct reset_control *rstc; - unsigned long max_delta; - int ret, bits, prescaler = 1; + unsigned long max_arr; struct timer_of *to; + int ret; to = kzalloc(sizeof(*to), GFP_KERNEL); if (!to) @@ -113,26 +113,21 @@ static int __init stm32_clockevent_init(struct device_node *node) /* Detect whether the timer is 16 or 32 bits */ writel_relaxed(~0U, timer_of_base(to) + TIM_ARR); - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR); - if (max_delta == ~0U) { - prescaler = 1; - bits = 32; - } else { - prescaler = 1024; - bits = 16; + max_arr = readl_relaxed(timer_of_base(to) + TIM_ARR); + if (max_arr != ~0U) { + pr_err("32 bits timer is needed\n"); + return -EINVAL; } + writel_relaxed(0, timer_of_base(to) + TIM_ARR); - writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC); + writel_relaxed(0, timer_of_base(to) + TIM_PSC); writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR); writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER); writel_relaxed(0, timer_of_base(to) + TIM_SR); clockevents_config_and_register(&to->clkevt, - timer_of_period(to), 0x60, max_delta); - - pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", - node, bits); + timer_of_period(to), 0x60, ~0U); return 0; }