gpio: grgpio: Do not use gc->pin2mask()

Message ID 20171020130347.26722-1-linus.walleij@linaro.org
State Accepted
Commit 5c7b0c4e7d5cd9850a93b8a1ea092baf4c8b3cd0
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Series
  • gpio: grgpio: Do not use gc->pin2mask()
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Commit Message

Linus Walleij Oct. 20, 2017, 1:03 p.m.
The pin2mask() accessor only shuffles BIT ORDER in big endian systems,
i.e. the bitstuffing is swizzled big endian so "bit 0" is bit 7 or
bit 15 or bit 31 or so.

The grgpio only uses big endian BYTE ORDER which will be taken car of
by the ->write_reg() callback.

Just use BIT(offset) to assign the bit.

Cc: Andreas Larsson <andreas@gaisler.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

---
 drivers/gpio/gpio-grgpio.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

-- 
2.13.6

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Comments

Andreas Larsson Oct. 20, 2017, 1:47 p.m. | #1
On 2017-10-20 15:03, Linus Walleij wrote:
> The pin2mask() accessor only shuffles BIT ORDER in big endian systems,

> i.e. the bitstuffing is swizzled big endian so "bit 0" is bit 7 or

> bit 15 or bit 31 or so.

>

> The grgpio only uses big endian BYTE ORDER which will be taken car of

> by the ->write_reg() callback.

>

> Just use BIT(offset) to assign the bit.


Sure, as bgpio_init is not called with BGPIOF_BIG_ENDIAN in the flags 
argument, the pin2mask call just resulted in a BIT(offset) anyway.

Acked-by: Andreas Larsson <andreas@gaisler.com>



> Cc: Andreas Larsson <andreas@gaisler.com>

> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

> ---

>   drivers/gpio/gpio-grgpio.c | 6 +++---

>   1 file changed, 3 insertions(+), 3 deletions(-)

>

> diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c

> index 6544a16ab02e..e2fc561f4315 100644

> --- a/drivers/gpio/gpio-grgpio.c

> +++ b/drivers/gpio/gpio-grgpio.c

> @@ -35,6 +35,7 @@

>   #include <linux/interrupt.h>

>   #include <linux/irq.h>

>   #include <linux/irqdomain.h>

> +#include <linux/bitops.h>

>

>   #define GRGPIO_MAX_NGPIO 32

>

> @@ -96,12 +97,11 @@ static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,

>   			     int val)

>   {

>   	struct gpio_chip *gc = &priv->gc;

> -	unsigned long mask = gc->pin2mask(gc, offset);

>

>   	if (val)

> -		priv->imask |= mask;

> +		priv->imask |= BIT(offset);

>   	else

> -		priv->imask &= ~mask;

> +		priv->imask &= ~BIT(offset);

>   	gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);

>   }

>

>


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Patch

diff --git a/drivers/gpio/gpio-grgpio.c b/drivers/gpio/gpio-grgpio.c
index 6544a16ab02e..e2fc561f4315 100644
--- a/drivers/gpio/gpio-grgpio.c
+++ b/drivers/gpio/gpio-grgpio.c
@@ -35,6 +35,7 @@ 
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/bitops.h>
 
 #define GRGPIO_MAX_NGPIO 32
 
@@ -96,12 +97,11 @@  static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
 			     int val)
 {
 	struct gpio_chip *gc = &priv->gc;
-	unsigned long mask = gc->pin2mask(gc, offset);
 
 	if (val)
-		priv->imask |= mask;
+		priv->imask |= BIT(offset);
 	else
-		priv->imask &= ~mask;
+		priv->imask &= ~BIT(offset);
 	gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
 }