From patchwork Mon Oct 23 09:58:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 116664 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp4451825qgn; Mon, 23 Oct 2017 02:59:50 -0700 (PDT) X-Received: by 10.84.174.4 with SMTP id q4mr10142933plb.233.1508752790842; Mon, 23 Oct 2017 02:59:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1508752790; cv=none; d=google.com; s=arc-20160816; b=eYkdjQkEeHBT9ZrTVmNENG9CDzPpkV5rUiL0B5tKEo8R9IK72WoGzzNCAwhHozYlHk dvrXMtFYriSSQrCrAhbIDDuHVlo8Avz3Gayc+n5wxUSGYCUdzbHOC/0vN2PSv+qYK6o0 sGofT/fNhZDSzZ1JuuvDNn9nP66aToLbTPtLsmNbI3li9R6f+xC03vAL3GG83ysZV43e 5X1YGUoliUnnlV6XHyVTqn1DwX2D41wcj7KPsHFxg8gevTI/zxyxdyaMntc84qDs9tdW ak6XdTh48cQra5xyPcuWJK4hib+3x+CSBgZxp4F00jY7eZMlmNjMNT/8xPE0t3z+e0z0 U2fQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=OSj6tMqg+qgSBNVmusePZKwkMQmgMUCbs9Mk0ysmC7k=; b=YLgOqVTOpl8On2si9ZOyVThwV9FhKvYqpHD3XxpM7/7+nL1Dr6MDPjo43Wtu57TLFN dbiCNhX/LRY47sZdrP0vvx7p7jvYfq3o9M7PI6/BEDFp25le7i4O+MzeFe8+r8TLG4Xi 5hgVQaWQAdryap5z6bDJv2b1KyvLZ/U5p7OkgMdo1WiAGWI9cG1TpTLod1GKfwcUzH9F ujya/WnWN05GPPqcfsOYtfQgYIdWslTwOdL71kgZ6jzttFwh8KEF3oylTihWvKin1w+P yuOcaxgC9SUvqKqPtFoAcYZuIEPO4gAfrjnPKVQ+yLUwkH8TLmfLruslJXF9U8bx3SGb 4nnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=N/Onrsnr; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b89si5088218pfd.354.2017.10.23.02.59.50; Mon, 23 Oct 2017 02:59:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=N/Onrsnr; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751405AbdJWJ7q (ORCPT + 6 others); Mon, 23 Oct 2017 05:59:46 -0400 Received: from mail-wr0-f196.google.com ([209.85.128.196]:49732 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751282AbdJWJ7p (ORCPT ); Mon, 23 Oct 2017 05:59:45 -0400 Received: by mail-wr0-f196.google.com with SMTP id g90so16698441wrd.6 for ; Mon, 23 Oct 2017 02:59:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tmtSr2/2KFY2IKM3M2bm/gYOBh5Ln7Q51D9HxqoTEVE=; b=N/OnrsnrnPxZf/Shlrq06Z7tuCIicxmYMuyqLVBrqT3xR18HDw6hbO0Sg8TKjNERxW 6AJnojEut+2TBa9ayNhGVwBGqJp+h/dgBHF0lNamSm3R6w5RG/hH1p8RSPEORex+db7v 6EVFpjxrJUjYkD9+boR25P7PLigfXKPI2FxX8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tmtSr2/2KFY2IKM3M2bm/gYOBh5Ln7Q51D9HxqoTEVE=; b=hxTU2pZ3USYX4D3R+66w4mLRm6wdV3Zydv8UtO9A1R2JjTam4Tec+Y9vWh4uM1g0eo +UUeUkBFr8zwnuL+Kmy0CJ2XkRFLZkJg0GlBd6TwrKvF9IQpq2v+1Btvu4xHuhJi0Q1u +SGt5W7GFLoC6UoRj3n7lCQehOqljCdPaOslS8aYaHKzeFRIywqLJkDzVrx0HmmEeFg1 kQqWJsnZog/4D6E825oE4/wFWCWYuWhBFBbpoVQ4aIaoLRqe8xDy3KSthjQvvXwAxAoQ wdLmguP5JIc6CtxI5ZcQABWj72oq2atmuVSIkzyhyYLFtkFXbWQ6ss30vGz0fybmEX8Y Zv4g== X-Gm-Message-State: AMCzsaVFHZig5SsIrPTBMnhkXPhIO078kp735Z/qQUJnSm/4YS2srLpq dEbwq4P9HqtUY2GuprrxVxz03A== X-Google-Smtp-Source: ABhQp+TsrcdttezTc2DFPBVLO5/V41Tm3cjqVzq0djnqTgHzvQGs8uLTWycQxZJyrs0U8lLLUFEgPw== X-Received: by 10.223.190.14 with SMTP id n14mr5644575wrh.46.1508752784114; Mon, 23 Oct 2017 02:59:44 -0700 (PDT) Received: from lmecxl0911.lme.st.com ([80.214.127.33]) by smtp.gmail.com with ESMTPSA id q188sm3626900wmb.43.2017.10.23.02.59.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Oct 2017 02:59:43 -0700 (PDT) From: Benjamin Gaignard To: robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, daniel.lezcano@linaro.org, tglx@linutronix.de, ludovic.barre@st.com, julien.thierry@arm.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Benjamin Gaignard Subject: [PATCH v7 3/6] clocksource: stm32: increase min delta value Date: Mon, 23 Oct 2017 11:58:39 +0200 Message-Id: <1508752722-4489-4-git-send-email-benjamin.gaignard@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1508752722-4489-1-git-send-email-benjamin.gaignard@linaro.org> References: <1508752722-4489-1-git-send-email-benjamin.gaignard@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The CPU is a CortexM4 @ 200MHZ and the clocks driving the timers are at 90MHZ with a min delta at 1 you could have an interrupt each 0.01 ms which is really to much. By increase it to 0x60 it give more time (around 1 ms) to CPU to handle the interrupt. Signed-off-by: Benjamin Gaignard --- drivers/clocksource/timer-stm32.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -- 2.7.4 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c index fc61fd1..dc9fee6 100644 --- a/drivers/clocksource/timer-stm32.c +++ b/drivers/clocksource/timer-stm32.c @@ -36,6 +36,8 @@ #define TIM_EGR_UG BIT(0) +#define MIN_DELTA 0x60 + static int stm32_clock_event_shutdown(struct clock_event_device *evt) { struct timer_of *to = to_timer_of(evt); @@ -129,7 +131,8 @@ static int __init stm32_clockevent_init(struct device_node *node) writel_relaxed(0, timer_of_base(to) + TIM_SR); clockevents_config_and_register(&to->clkevt, - timer_of_period(to), 0x1, max_delta); + timer_of_period(to), + MIN_DELTA, max_delta); pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n", node, bits);