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[209.132.180.67]) by mx.google.com with ESMTP id u23si5839509plk.787.2017.10.29.06.49.52; Sun, 29 Oct 2017 06:49:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ATcfCt77; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751908AbdJ2Ntu (ORCPT + 27 others); Sun, 29 Oct 2017 09:49:50 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:57240 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751830AbdJ2Ntm (ORCPT ); Sun, 29 Oct 2017 09:49:42 -0400 Received: by mail-pg0-f65.google.com with SMTP id m18so9101050pgd.13 for ; Sun, 29 Oct 2017 06:49:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=bVJe14EBdiFFBbA8qLcbwY4uEd5vnP2Um/7UVfi0rzY=; b=ATcfCt77CEzuX5W52njuP3+SILlYu65WgCcjigXmDt3RQ6wAfhhBUdMoDwfe2lIjwd yGZyAddFbgoFxDAGDwTNNy4vgpTUoFlT7Qj+VNsIoXyuK6bDWVv7Q/CnKSccK+cw2gJH yd+AjaN/qQaySpHqOg+t1W+LFGVETUc65uH60= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=bVJe14EBdiFFBbA8qLcbwY4uEd5vnP2Um/7UVfi0rzY=; b=Qae5PzukVQvatWGhKJ/Oz2SKQfQmreGQH/tPJy3sDzRA+9zSPE+AplcoXXTJiR7CA0 MI3LSDug5HEDRu2uWAJX4m6Yi8FNfPmaxwyBOGoLon+fWfggh92griVTjp36DlJePapV /L+hm2kmI6WEwNADYYDhjzbpNc2hOJ3X+w/Q8W/mYLqrtjmBQgIIgcG3o3IafW0OD2ui CjuvOSciUWrg3KrwnItN4pMZ4OgDA+wL4n6zDExZ1FQlenzTcT5TzJ/Lv9eRPBHUfEvp 2twItqx/20cdwungvOGEXM63xXFqAA2jlHMjBZGW0eklXne3MC0FxCkeQP14nplECtkH CKLg== X-Gm-Message-State: AMCzsaW05nZj0+D9224oijJDu4B+4jg/CRXsrMmicmlyjQk1cGdxWu+W Ihx3el1jij+djX990+MwYlBkqg== X-Received: by 10.84.218.68 with SMTP id f4mr4763136plm.395.1509284982001; Sun, 29 Oct 2017 06:49:42 -0700 (PDT) Received: from localhost ([122.167.161.211]) by smtp.gmail.com with ESMTPSA id 81sm25482565pfh.145.2017.10.29.06.49.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 29 Oct 2017 06:49:41 -0700 (PDT) From: Viresh Kumar To: Greg Kroah-Hartman Cc: Viresh Kumar , Vincent Guittot , Stephen Boyd , Rajendra Nayak , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, robdclark@gmail.com, s.hauer@pengutronix.de, l.stach@pengutronix.de, shawnguo@kernel.org, fabio.estevam@nxp.com, nm@ti.com, xuwei5@hisilicon.com, robh+dt@kernel.org Subject: [PATCH V4 12/12] boot_constraint: Add Qualcomm display controller constraints Date: Sun, 29 Oct 2017 19:19:00 +0530 Message-Id: X-Mailer: git-send-email 2.15.0.rc1.236.g92ea95045093 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Rajendra Nayak This sets boot constraints for the display controller used on Qualcomm dragonboard 410c. The display controlled is enabled by the bootloader to show a flash screen during kernel boot. The handover to kernel should be without any glitches on the screen.The resources of the display controller (like regulators) are shared with other peripherals, which may reconfigure those resources before the display driver comes up. The same problem can happen if the display driver probes first, as the constraints of the other devices (sharing same resources with display controller) may not be honored anymore by the kernel. Signed-off-by: Rajendra Nayak Signed-off-by: Viresh Kumar --- arch/arm64/Kconfig.platforms | 1 + drivers/boot_constraints/Makefile | 1 + drivers/boot_constraints/qcom.c | 123 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 125 insertions(+) create mode 100644 drivers/boot_constraints/qcom.c -- 2.15.0.rc1.236.g92ea95045093 diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 265df4a088ab..6343627cf105 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -134,6 +134,7 @@ config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB select PINCTRL + select DEV_BOOT_CONSTRAINTS help This enables support for the ARMv8 based Qualcomm chipsets. diff --git a/drivers/boot_constraints/Makefile b/drivers/boot_constraints/Makefile index 3b5a87fcf099..e32751b70957 100644 --- a/drivers/boot_constraints/Makefile +++ b/drivers/boot_constraints/Makefile @@ -4,3 +4,4 @@ obj-y := clk.o deferrable_dev.o core.o pm.o serial.o supply.o obj-$(CONFIG_ARCH_HISI) += hikey.o obj-$(CONFIG_ARCH_MXC) += imx.o +obj-$(CONFIG_ARCH_QCOM) += qcom.o diff --git a/drivers/boot_constraints/qcom.c b/drivers/boot_constraints/qcom.c new file mode 100644 index 000000000000..e89357670906 --- /dev/null +++ b/drivers/boot_constraints/qcom.c @@ -0,0 +1,123 @@ +/* + * This sets up Dragonboard 410c constraints on behalf of the bootloader, which + * uses display controller to display a flash screen during system boot. + * + * Copyright (C) 2017 Linaro. + * Viresh Kumar + * Rajendra Nayak + * + * This file is released under the GPLv2. + */ + +#include +#include +#include +#include + +static struct dev_boot_constraint_clk_info iface_clk_info = { + .name = "iface_clk", +}; + +static struct dev_boot_constraint_clk_info bus_clk_info = { + .name = "bus_clk", +}; + +static struct dev_boot_constraint_clk_info core_clk_info = { + .name = "core_clk", +}; + +static struct dev_boot_constraint_clk_info vsync_clk_info = { + .name = "vsync_clk", +}; + +static struct dev_boot_constraint_clk_info esc0_clk_info = { + .name = "core_clk", +}; + +static struct dev_boot_constraint_clk_info byte_clk_info = { + .name = "byte_clk", +}; + +static struct dev_boot_constraint_clk_info pixel_clk_info = { + .name = "pixel_clk", +}; + +static struct dev_boot_constraint_supply_info vdda_info = { + .name = "vdda" +}; + +static struct dev_boot_constraint_supply_info vddio_info = { + .name = "vddio" +}; + +static struct dev_boot_constraint constraints_mdss[] = { + { + .type = DEV_BOOT_CONSTRAINT_PM, + .data = NULL, + }, +}; + +static struct dev_boot_constraint constraints_mdp[] = { + { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &iface_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &bus_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &core_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &vsync_clk_info, + }, +}; + +static struct dev_boot_constraint constraints_dsi[] = { + { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &esc0_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &byte_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_CLK, + .data = &pixel_clk_info, + }, { + .type = DEV_BOOT_CONSTRAINT_SUPPLY, + .data = &vdda_info, + + }, { + .type = DEV_BOOT_CONSTRAINT_SUPPLY, + .data = &vddio_info, + }, +}; + +static struct dev_boot_constraint_of constraints[] = { + { + .compat = "qcom,mdss", + .constraints = constraints_mdss, + .count = ARRAY_SIZE(constraints_mdss), + }, { + .compat = "qcom,mdp5", + .constraints = constraints_mdp, + .count = ARRAY_SIZE(constraints_mdp), + }, { + .compat = "qcom,mdss-dsi-ctrl", + .constraints = constraints_dsi, + .count = ARRAY_SIZE(constraints_dsi), + }, +}; + +static int __init qcom_constraints_init(void) +{ + /* Only Dragonboard 410c is supported for now */ + if (!of_machine_is_compatible("qcom,apq8016-sbc")) + return 0; + + dev_boot_constraint_add_deferrable_of(constraints, + ARRAY_SIZE(constraints)); + + return 0; +} +subsys_initcall(qcom_constraints_init);