From patchwork Mon Oct 30 13:04:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 117480 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp2564970qgn; Mon, 30 Oct 2017 06:06:29 -0700 (PDT) X-Google-Smtp-Source: ABhQp+TqXrtIu3+dmu1vXH+EnRBn3Am1KRdoi3QzP4z97wZFA22NvCO3f5MbhqZ64DZ+w1IhtGW+ X-Received: by 10.98.82.85 with SMTP id g82mr8789088pfb.31.1509368789265; Mon, 30 Oct 2017 06:06:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509368789; cv=none; d=google.com; s=arc-20160816; b=tNU/lyROzqw0ZLHm7ajXnmdwKy0me9JoPUo2XTBevuqdVaYPz6D/uDsMBwi1qlcalR 1GPUGyr20nF6zgsAK3oKWcQWxynspbVl2fR8lCd7p3Ykyb+M0VRgTVSW/WaT2cmgf447 uF5PH4f4+IPRgpJyoIbodCfquqiChCPtF+SwlKaH9R08O9ISKii+IPlABLPOsI1eycki DRe8anYDcHxuBCq/eHVp7znlbDeXOdEs55BgTdP+TmNN+LPWWu+K2KyUQNaV2DFxbYtf iS/G0kU4dzU1lX92FsdfN1WlVuT587+cpM3M1MDHTHo5t+E3Pl9d27W79oQKRBFzaw3e OC+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature :arc-authentication-results; bh=EMaBUzEzDdUyykF+b03BBn8BlRjdTC2PoqoPD4Wpa3k=; b=bNEt7sB7X2ASqulsxrWfZdWWxcnRTsiQgUhFgHRNe/0EtChyq8l+VPQE++tiCXSUtv LkW9R1iZ6efipuY+jMXn3YE1LOBBVRNcRpXwLoeqgruf4ZQ/7nDhuU5WNdtTVhVMEUwo TyhntlfQVql2fGAhO/h9M0DAETEwNE5bY3L0IcsHIChsGPcTZG+0AZPuZyU2aGDp9i0H oqrICK4tOOoGztgs+CCsXH84KKlREgjVhILb9jp7Gw9qoqBLGw4S4EaxW48eFWb+xQdn xAWjR7NzLSbHez3iYbb6yHiEejbbWUVkPrIfNywJJ4u3KODCEi9G8IdiQaCTjuBACJJ0 7KCQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=epYzZNSo; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s21si2466642plr.463.2017.10.30.06.06.29; Mon, 30 Oct 2017 06:06:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=epYzZNSo; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752367AbdJ3NG1 (ORCPT + 4 others); Mon, 30 Oct 2017 09:06:27 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:21674 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752352AbdJ3NGZ (ORCPT ); Mon, 30 Oct 2017 09:06:25 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v9UD6M6B013396; Mon, 30 Oct 2017 08:06:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1509368782; bh=Lrqfq5j0Y7VRCjxOCvdNdASh23AMOMOqEhHtsahXm18=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=epYzZNSoDt9YvTNWzOaMy8DlhQ7gZshtnzphjbNADh1kGlXAaw2b7jNFdgwjZ7hPo vYkvM8m4P2up2wUK3TN9Bn3cM4RHLwoDxWv0tcXGgXC25Op0pBBTVKu8CJDgEWNkPE TnKCFQfG3/FT1M1whRNpwH0i5Rx+S6zBMcAZ0RM8= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9UD6Msr018952; Mon, 30 Oct 2017 08:06:22 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34; Mon, 30 Oct 2017 08:06:22 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend Transport; Mon, 30 Oct 2017 08:06:21 -0500 Received: from gomoku.home (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v9UD54xF005221; Mon, 30 Oct 2017 08:06:20 -0500 From: Tero Kristo To: , , CC: , Subject: [PATCH 24/27] clk: ti: dm814: add clkctrl clock data Date: Mon, 30 Oct 2017 15:04:42 +0200 Message-ID: <1509368685-29112-25-git-send-email-t-kristo@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509368685-29112-1-git-send-email-t-kristo@ti.com> References: <1509368685-29112-1-git-send-email-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add data for dm814 clkctrl clocks, and register it within the clkctrl driver. Signed-off-by: Tero Kristo --- drivers/clk/ti/clk-814x.c | 37 +++++++++++++++++++++++++++++++++++++ drivers/clk/ti/clkctrl.c | 4 ++++ drivers/clk/ti/clock.h | 1 + 3 files changed, 42 insertions(+) -- 1.9.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/ti/clk-814x.c b/drivers/clk/ti/clk-814x.c index 7dab941..f688fdd 100644 --- a/drivers/clk/ti/clk-814x.c +++ b/drivers/clk/ti/clk-814x.c @@ -9,9 +9,46 @@ #include #include #include +#include #include "clock.h" +static const struct omap_clkctrl_reg_data dm814_default_clkctrl_regs[] __initconst = { + { DM814_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "pll260dcoclkldo" }, + { 0 }, +}; + +static const struct omap_clkctrl_reg_data dm814_alwon_clkctrl_regs[] __initconst = { + { DM814_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM814_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM814_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM814_GPIO1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, + { DM814_GPIO2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, + { DM814_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM814_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM814_WD_TIMER_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" }, + { DM814_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk10_ck" }, + { DM814_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk6_ck" }, + { DM814_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk" }, + { DM814_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "mpu_ck" }, + { DM814_RTC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_NO_IDLEST, "sysclk18_ck" }, + { DM814_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, + { DM814_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, + { DM814_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, + { DM814_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, + { DM814_TPTC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk4_ck" }, + { DM814_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" }, + { DM814_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" }, + { DM814_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "sysclk8_ck" }, + { 0 }, +}; + +const struct omap_clkctrl_data dm814_clkctrl_data[] __initconst = { + { 0x48180500, dm814_default_clkctrl_regs }, + { 0x48181400, dm814_alwon_clkctrl_regs }, + { 0 }, +}; + static struct ti_dt_clk dm814_clks[] = { DT_CLK(NULL, "timer_sys_ck", "devosc_ck"), { .node_name = NULL }, diff --git a/drivers/clk/ti/clkctrl.c b/drivers/clk/ti/clkctrl.c index 74d1320..a531a89 100644 --- a/drivers/clk/ti/clkctrl.c +++ b/drivers/clk/ti/clkctrl.c @@ -453,6 +453,10 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) if (of_machine_is_compatible("ti,am4372")) data = am4_clkctrl_data; #endif +#ifdef CONFIG_SOC_TI81XX + if (of_machine_is_compatible("ti,dm814")) + data = dm814_clkctrl_data; +#endif while (data->addr) { if (addr == data->addr) diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index a42bbb8..60e6794 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -235,6 +235,7 @@ struct omap_clkctrl_data { extern const struct omap_clkctrl_data dra7_clkctrl_data[]; extern const struct omap_clkctrl_data am3_clkctrl_data[]; extern const struct omap_clkctrl_data am4_clkctrl_data[]; +extern const struct omap_clkctrl_data dm814_clkctrl_data[]; #define CLKF_SW_SUP BIT(0) #define CLKF_HW_SUP BIT(1)