| Message ID | 1509993206-26637-3-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | Accepted |
| Headers | show |
| Series | linux-user: fix various SIGSEGV delivery bugs | expand |
Le 06/11/2017 à 19:33, Peter Maydell a écrit : > For faults on loads and stores, ppc_cpu_handle_mmu_fault() in > target/ppc/user_only_helper.c stores the offending address > in env->spr[SPR_DAR]. Report this correctly to the guest > in si_addr, rather than incorrectly using the address of the > instruction that caused the fault. > > This fixes the test case in > https://bugs.launchpad.net/qemu/+bug/1077116 > for ppc, ppc64 and ppc64le. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > linux-user/main.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/linux-user/main.c b/linux-user/main.c > index b6dd9ef..6286661 100644 > --- a/linux-user/main.c > +++ b/linux-user/main.c > @@ -1420,7 +1420,7 @@ void cpu_loop(CPUPPCState *env) > info.si_code = TARGET_SEGV_MAPERR; > break; > } > - info._sifields._sigfault._addr = env->nip; > + info._sifields._sigfault._addr = env->spr[SPR_DAR]; > queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); > break; > case POWERPC_EXCP_ISI: /* Instruction storage exception */ > Reviewed-by: Laurent Vivier <laurent@vivier.eu>
On 11/06/2017 07:33 PM, Peter Maydell wrote: > For faults on loads and stores, ppc_cpu_handle_mmu_fault() in > target/ppc/user_only_helper.c stores the offending address > in env->spr[SPR_DAR]. Report this correctly to the guest > in si_addr, rather than incorrectly using the address of the > instruction that caused the fault. > > This fixes the test case in > https://bugs.launchpad.net/qemu/+bug/1077116 > for ppc, ppc64 and ppc64le. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > linux-user/main.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/linux-user/main.c b/linux-user/main.c index b6dd9ef..6286661 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -1420,7 +1420,7 @@ void cpu_loop(CPUPPCState *env) info.si_code = TARGET_SEGV_MAPERR; break; } - info._sifields._sigfault._addr = env->nip; + info._sifields._sigfault._addr = env->spr[SPR_DAR]; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; case POWERPC_EXCP_ISI: /* Instruction storage exception */
For faults on loads and stores, ppc_cpu_handle_mmu_fault() in target/ppc/user_only_helper.c stores the offending address in env->spr[SPR_DAR]. Report this correctly to the guest in si_addr, rather than incorrectly using the address of the instruction that caused the fault. This fixes the test case in https://bugs.launchpad.net/qemu/+bug/1077116 for ppc, ppc64 and ppc64le. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- linux-user/main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.7.4