| Message ID | 87k1z0x0l6.fsf@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | Add SVE support for load/store_lanes | expand |
Ping Richard Sandiford <richard.sandiford@linaro.org> writes: > This patch adds tests for the SVE structure mode move patterns > and for LD[234] and ST[234] vectorisation. > > > 2017-11-08 Richard Sandiford <richard.sandiford@linaro.org> > Alan Hayward <alan.hayward@arm.com> > David Sherwood <david.sherwood@arm.com> > > gcc/testsuite/ > * gcc.target/aarch64/sve_struct_move_1.c: New test. > * gcc.target/aarch64/sve_struct_move_2.c: Likewise. > * gcc.target/aarch64/sve_struct_move_3.c: Likewise. > * gcc.target/aarch64/sve_struct_move_4.c: Likewise. > * gcc.target/aarch64/sve_struct_move_5.c: Likewise. > * gcc.target/aarch64/sve_struct_move_6.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_1.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_1_run.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_2.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_2_run.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_3.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_3_run.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_4.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_4_run.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_5.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_5_run.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_6.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_6_run.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_7.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_7_run.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_8.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_8_run.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_9.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_9_run.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_10.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_10_run.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_11.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_11_run.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_12.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_12_run.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_13.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_13_run.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_14.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_15.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_16.c: Likewise. > * gcc.target/aarch64/sve_struct_vect_17.c: Likewise. Index: gcc/testsuite/gcc.target/aarch64/sve_struct_move_1.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_move_1.c 2017-11-08 15:06:27.247849138 +0000 @@ -0,0 +1,129 @@ +/* { dg-do assemble } */ +/* { dg-options "-O -march=armv8-a+sve -msve-vector-bits=256 -mbig-endian --save-temps" } */ + +typedef char v32qi __attribute__((vector_size(32))); +typedef struct { v32qi a[2]; } v64qi; + +typedef short v16hi __attribute__((vector_size(32))); +typedef struct { v16hi a[2]; } v32hi; + +typedef int v8si __attribute__((vector_size(32))); +typedef struct { v8si a[2]; } v16si; + +typedef long v4di __attribute__((vector_size(32))); +typedef struct { v4di a[2]; } v8di; + +typedef _Float16 v16hf __attribute__((vector_size(32))); +typedef struct { v16hf a[2]; } v32hf; + +typedef float v8sf __attribute__((vector_size(32))); +typedef struct { v8sf a[2]; } v16sf; + +typedef double v4df __attribute__((vector_size(32))); +typedef struct { v4df a[2]; } v8df; + +#define TEST_TYPE(TYPE, REG1, REG2) \ + void \ + f1_##TYPE (TYPE *a) \ + { \ + register TYPE x asm (#REG1) = a[0]; \ + asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \ + register TYPE y asm (#REG2) = x; \ + asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2" \ + : "=&w" (x) : "0" (x), "w" (y)); \ + a[1] = x; \ + } \ + /* This must compile, but we don't care how. */ \ + void \ + f2_##TYPE (TYPE *a) \ + { \ + TYPE x = a[0]; \ + x.a[0][3] = 1; \ + x.a[1][2] = 12; \ + asm volatile ("# %0" :: "w" (x)); \ + } \ + void \ + f3_##TYPE (TYPE *a, int i) \ + { \ + TYPE x = a[0]; \ + x.a[0][i] = 1; \ + asm volatile ("# %0" :: "w" (x)); \ + } \ + void \ + f4_##TYPE (TYPE *a, int i, int j) \ + { \ + TYPE x = a[0]; \ + x.a[i][j] = 44; \ + asm volatile ("# %0" :: "w" (x)); \ + } + +TEST_TYPE (v64qi, z0, z2) +TEST_TYPE (v32hi, z5, z7) +TEST_TYPE (v16si, z10, z12) +TEST_TYPE (v8di, z15, z17) +TEST_TYPE (v32hf, z18, z20) +TEST_TYPE (v16sf, z21, z23) +TEST_TYPE (v8df, z28, z30) + +/* { dg-final { scan-assembler {\tld1b\tz0.b, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1b\tz1.b, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v64qi 1 z0\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z0.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z1.d\n} } } */ +/* { dg-final { scan-assembler { test v64qi 2 z0, z0, z2\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz0.b, p[0-7], \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz1.b, p[0-7], \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1h\tz5.h, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz6.h, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v32hi 1 z5\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz7.d, z5.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz8.d, z6.d\n} } } */ +/* { dg-final { scan-assembler { test v32hi 2 z5, z5, z7\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz5.h, p[0-7], \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz6.h, p[0-7], \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1w\tz10.s, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz11.s, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16si 1 z10\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz12.d, z10.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz13.d, z11.d\n} } } */ +/* { dg-final { scan-assembler { test v16si 2 z10, z10, z12\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz10.s, p[0-7], \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz11.s, p[0-7], \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1d\tz15.d, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz16.d, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v8di 1 z15\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z15.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz18.d, z16.d\n} } } */ +/* { dg-final { scan-assembler { test v8di 2 z15, z15, z17\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz15.d, p[0-7], \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz16.d, p[0-7], \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1h\tz18.h, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz19.h, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v32hf 1 z18\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz20.d, z18.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz21.d, z19.d\n} } } */ +/* { dg-final { scan-assembler { test v32hf 2 z18, z18, z20\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz18.h, p[0-7], \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz19.h, p[0-7], \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1w\tz21.s, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz22.s, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16sf 1 z21\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz23.d, z21.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz24.d, z22.d\n} } } */ +/* { dg-final { scan-assembler { test v16sf 2 z21, z21, z23\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz21.s, p[0-7], \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz22.s, p[0-7], \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1d\tz28.d, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz29.d, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v8df 1 z28\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz30.d, z28.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz31.d, z29.d\n} } } */ +/* { dg-final { scan-assembler { test v8df 2 z28, z28, z30\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz28.d, p[0-7], \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz29.d, p[0-7], \[x0, #3, mul vl\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_move_2.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_move_2.c 2017-11-08 15:06:27.247849138 +0000 @@ -0,0 +1,127 @@ +/* { dg-do assemble } */ +/* { dg-options "-O -march=armv8-a+sve -msve-vector-bits=256 -mbig-endian --save-temps" } */ + +typedef char v32qi __attribute__((vector_size(32))); +typedef struct { v32qi a[3]; } v96qi; + +typedef short v16hi __attribute__((vector_size(32))); +typedef struct { v16hi a[3]; } v48hi; + +typedef int v8si __attribute__((vector_size(32))); +typedef struct { v8si a[3]; } v24si; + +typedef long v4di __attribute__((vector_size(32))); +typedef struct { v4di a[3]; } v12di; + +typedef _Float16 v16hf __attribute__((vector_size(32))); +typedef struct { v16hf a[3]; } v48hf; + +typedef float v8sf __attribute__((vector_size(32))); +typedef struct { v8sf a[3]; } v24sf; + +typedef double v4df __attribute__((vector_size(32))); +typedef struct { v4df a[3]; } v12df; + +#define TEST_TYPE(TYPE, REG1, REG2) \ + void \ + f_##TYPE (TYPE *a) \ + { \ + register TYPE x asm (#REG1) = a[0]; \ + asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \ + register TYPE y asm (#REG2) = x; \ + asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2" \ + : "=&w" (x) : "0" (x), "w" (y)); \ + a[1] = x; \ + } + +TEST_TYPE (v96qi, z0, z3) +TEST_TYPE (v48hi, z6, z2) +TEST_TYPE (v24si, z12, z15) +TEST_TYPE (v12di, z16, z13) +TEST_TYPE (v48hf, z18, z1) +TEST_TYPE (v24sf, z20, z23) +TEST_TYPE (v12df, z26, z29) + +/* { dg-final { scan-assembler {\tld1b\tz0.b, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1b\tz1.b, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1b\tz2.b, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v96qi 1 z0\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z0.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z1.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz5.d, z2.d\n} } } */ +/* { dg-final { scan-assembler { test v96qi 2 z0, z0, z3\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz0.b, p[0-7], \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz1.b, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz2.b, p[0-7], \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1h\tz6.h, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz7.h, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz8.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v48hi 1 z6\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z6.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z7.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z8.d\n} } } */ +/* { dg-final { scan-assembler { test v48hi 2 z6, z6, z2\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz6.h, p[0-7], \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz7.h, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz8.h, p[0-7], \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1w\tz12.s, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz13.s, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz14.s, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v24si 1 z12\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz15.d, z12.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z13.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z14.d\n} } } */ +/* { dg-final { scan-assembler { test v24si 2 z12, z12, z15\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz12.s, p[0-7], \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz13.s, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz14.s, p[0-7], \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1d\tz16.d, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz17.d, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz18.d, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v12di 1 z16\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz13.d, z16.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz14.d, z17.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz15.d, z18.d\n} } } */ +/* { dg-final { scan-assembler { test v12di 2 z16, z16, z13\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz16.d, p[0-7], \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz17.d, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz18.d, p[0-7], \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1h\tz18.h, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz19.h, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz20.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v48hf 1 z18\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz1.d, z18.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z19.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z20.d\n} } } */ +/* { dg-final { scan-assembler { test v48hf 2 z18, z18, z1\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz18.h, p[0-7], \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz19.h, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz20.h, p[0-7], \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1w\tz20.s, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz21.s, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz22.s, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v24sf 1 z20\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz23.d, z20.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz24.d, z21.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz25.d, z22.d\n} } } */ +/* { dg-final { scan-assembler { test v24sf 2 z20, z20, z23\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz20.s, p[0-7], \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz21.s, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz22.s, p[0-7], \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1d\tz26.d, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz27.d, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz28.d, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v12df 1 z26\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz29.d, z26.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz30.d, z27.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz31.d, z28.d\n} } } */ +/* { dg-final { scan-assembler { test v12df 2 z26, z26, z29\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz26.d, p[0-7], \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz27.d, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz28.d, p[0-7], \[x0, #5, mul vl\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_move_3.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_move_3.c 2017-11-08 15:06:27.247849138 +0000 @@ -0,0 +1,148 @@ +/* { dg-do assemble } */ +/* { dg-options "-O -march=armv8-a+sve -msve-vector-bits=256 -mbig-endian --save-temps" } */ + +typedef char v32qi __attribute__((vector_size(32))); +typedef struct { v32qi a[4]; } v128qi; + +typedef short v16hi __attribute__((vector_size(32))); +typedef struct { v16hi a[4]; } v64hi; + +typedef int v8si __attribute__((vector_size(32))); +typedef struct { v8si a[4]; } v32si; + +typedef long v4di __attribute__((vector_size(32))); +typedef struct { v4di a[4]; } v16di; + +typedef _Float16 v16hf __attribute__((vector_size(32))); +typedef struct { v16hf a[4]; } v64hf; + +typedef float v8sf __attribute__((vector_size(32))); +typedef struct { v8sf a[4]; } v32sf; + +typedef double v4df __attribute__((vector_size(32))); +typedef struct { v4df a[4]; } v16df; + +#define TEST_TYPE(TYPE, REG1, REG2) \ + void \ + f_##TYPE (TYPE *a) \ + { \ + register TYPE x asm (#REG1) = a[0]; \ + asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \ + register TYPE y asm (#REG2) = x; \ + asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2" \ + : "=&w" (x) : "0" (x), "w" (y)); \ + a[1] = x; \ + } + +TEST_TYPE (v128qi, z0, z4) +TEST_TYPE (v64hi, z6, z2) +TEST_TYPE (v32si, z12, z16) +TEST_TYPE (v16di, z17, z13) +TEST_TYPE (v64hf, z18, z1) +TEST_TYPE (v32sf, z20, z16) +TEST_TYPE (v16df, z24, z28) + +/* { dg-final { scan-assembler {\tld1b\tz0.b, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1b\tz1.b, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1b\tz2.b, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1b\tz3.b, p[0-7]/z, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v128qi 1 z0\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z0.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz5.d, z1.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz6.d, z2.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz7.d, z3.d\n} } } */ +/* { dg-final { scan-assembler { test v128qi 2 z0, z0, z4\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz0.b, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz1.b, p[0-7], \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz2.b, p[0-7], \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz3.b, p[0-7], \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1h\tz6.h, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz7.h, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz8.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz9.h, p[0-7]/z, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v64hi 1 z6\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z6.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z7.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z8.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz5.d, z9.d\n} } } */ +/* { dg-final { scan-assembler { test v64hi 2 z6, z6, z2\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz6.h, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz7.h, p[0-7], \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz8.h, p[0-7], \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz9.h, p[0-7], \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1w\tz12.s, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz13.s, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz14.s, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz15.s, p[0-7]/z, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v32si 1 z12\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z12.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z13.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz18.d, z14.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz19.d, z15.d\n} } } */ +/* { dg-final { scan-assembler { test v32si 2 z12, z12, z16\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz12.s, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz13.s, p[0-7], \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz14.s, p[0-7], \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz15.s, p[0-7], \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1d\tz17.d, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz18.d, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz19.d, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz20.d, p[0-7]/z, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16di 1 z17\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz13.d, z17.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz14.d, z18.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz15.d, z19.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z20.d\n} } } */ +/* { dg-final { scan-assembler { test v16di 2 z17, z17, z13\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz17.d, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz18.d, p[0-7], \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz19.d, p[0-7], \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz20.d, p[0-7], \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1h\tz18.h, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz19.h, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz20.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz21.h, p[0-7]/z, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v64hf 1 z18\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz1.d, z18.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z19.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z20.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z21.d\n} } } */ +/* { dg-final { scan-assembler { test v64hf 2 z18, z18, z1\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz18.h, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz19.h, p[0-7], \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz20.h, p[0-7], \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz21.h, p[0-7], \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1w\tz20.s, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz21.s, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz22.s, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz23.s, p[0-7]/z, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v32sf 1 z20\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z20.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z21.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz18.d, z22.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz19.d, z23.d\n} } } */ +/* { dg-final { scan-assembler { test v32sf 2 z20, z20, z16\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz20.s, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz21.s, p[0-7], \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz22.s, p[0-7], \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz23.s, p[0-7], \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1d\tz24.d, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz25.d, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz26.d, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz27.d, p[0-7]/z, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16df 1 z24\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz28.d, z24.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz29.d, z25.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz30.d, z26.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz31.d, z27.d\n} } } */ +/* { dg-final { scan-assembler { test v16df 2 z24, z24, z28\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz24.d, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz25.d, p[0-7], \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz26.d, p[0-7], \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz27.d, p[0-7], \[x0, #7, mul vl\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_move_4.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_move_4.c 2017-11-08 15:06:27.247849138 +0000 @@ -0,0 +1,116 @@ +/* { dg-do assemble } */ +/* { dg-options "-O -march=armv8-a+sve -msve-vector-bits=256 -mlittle-endian --save-temps" } */ + +typedef char v32qi __attribute__((vector_size(32))); +typedef struct { v32qi a[2]; } v64qi; + +typedef short v16hi __attribute__((vector_size(32))); +typedef struct { v16hi a[2]; } v32hi; + +typedef int v8si __attribute__((vector_size(32))); +typedef struct { v8si a[2]; } v16si; + +typedef long v4di __attribute__((vector_size(32))); +typedef struct { v4di a[2]; } v8di; + +typedef float v8sf __attribute__((vector_size(32))); +typedef struct { v8sf a[2]; } v16sf; + +typedef double v4df __attribute__((vector_size(32))); +typedef struct { v4df a[2]; } v8df; + +#define TEST_TYPE(TYPE, REG1, REG2) \ + void \ + f1_##TYPE (TYPE *a) \ + { \ + register TYPE x asm (#REG1) = a[0]; \ + asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \ + register TYPE y asm (#REG2) = x; \ + asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2" \ + : "=&w" (x) : "0" (x), "w" (y)); \ + a[1] = x; \ + } \ + /* This must compile, but we don't care how. */ \ + void \ + f2_##TYPE (TYPE *a) \ + { \ + TYPE x = a[0]; \ + x.a[0][3] = 1; \ + x.a[1][2] = 12; \ + asm volatile ("# %0" :: "w" (x)); \ + } \ + void \ + f3_##TYPE (TYPE *a, int i) \ + { \ + TYPE x = a[0]; \ + x.a[0][i] = 1; \ + asm volatile ("# %0" :: "w" (x)); \ + } \ + void \ + f4_##TYPE (TYPE *a, int i, int j) \ + { \ + TYPE x = a[0]; \ + x.a[i][j] = 44; \ + asm volatile ("# %0" :: "w" (x)); \ + } + +TEST_TYPE (v64qi, z0, z2) +TEST_TYPE (v32hi, z5, z7) +TEST_TYPE (v16si, z10, z12) +TEST_TYPE (v8di, z15, z17) +TEST_TYPE (v16sf, z20, z23) +TEST_TYPE (v8df, z28, z30) + +/* { dg-final { scan-assembler {\tldr\tz0, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz1, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v64qi 1 z0\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z0.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z1.d\n} } } */ +/* { dg-final { scan-assembler { test v64qi 2 z0, z0, z2\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz0, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz1, \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz5, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz6, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v32hi 1 z5\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz7.d, z5.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz8.d, z6.d\n} } } */ +/* { dg-final { scan-assembler { test v32hi 2 z5, z5, z7\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz5, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz6, \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz10, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz11, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16si 1 z10\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz12.d, z10.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz13.d, z11.d\n} } } */ +/* { dg-final { scan-assembler { test v16si 2 z10, z10, z12\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz10, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz11, \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz15, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz16, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v8di 1 z15\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z15.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz18.d, z16.d\n} } } */ +/* { dg-final { scan-assembler { test v8di 2 z15, z15, z17\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz15, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz16, \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz20, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz21, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16sf 1 z20\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz23.d, z20.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz24.d, z21.d\n} } } */ +/* { dg-final { scan-assembler { test v16sf 2 z20, z20, z23\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz20, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz21, \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz28, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz29, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v8df 1 z28\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz30.d, z28.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz31.d, z29.d\n} } } */ +/* { dg-final { scan-assembler { test v8df 2 z28, z28, z30\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz28, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz29, \[x0, #3, mul vl\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_move_5.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_move_5.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,111 @@ +/* { dg-do assemble } */ +/* { dg-options "-O -march=armv8-a+sve -msve-vector-bits=256 -mlittle-endian --save-temps" } */ + +typedef char v32qi __attribute__((vector_size(32))); +typedef struct { v32qi a[3]; } v96qi; + +typedef short v16hi __attribute__((vector_size(32))); +typedef struct { v16hi a[3]; } v48hi; + +typedef int v8si __attribute__((vector_size(32))); +typedef struct { v8si a[3]; } v24si; + +typedef long v4di __attribute__((vector_size(32))); +typedef struct { v4di a[3]; } v12di; + +typedef float v8sf __attribute__((vector_size(32))); +typedef struct { v8sf a[3]; } v24sf; + +typedef double v4df __attribute__((vector_size(32))); +typedef struct { v4df a[3]; } v12df; + +#define TEST_TYPE(TYPE, REG1, REG2) \ + void \ + f_##TYPE (TYPE *a) \ + { \ + register TYPE x asm (#REG1) = a[0]; \ + asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \ + register TYPE y asm (#REG2) = x; \ + asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2" \ + : "=&w" (x) : "0" (x), "w" (y)); \ + a[1] = x; \ + } + +TEST_TYPE (v96qi, z0, z3) +TEST_TYPE (v48hi, z6, z2) +TEST_TYPE (v24si, z12, z15) +TEST_TYPE (v12di, z16, z13) +TEST_TYPE (v24sf, z20, z23) +TEST_TYPE (v12df, z26, z29) + +/* { dg-final { scan-assembler {\tldr\tz0, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz1, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz2, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v96qi 1 z0\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z0.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z1.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz5.d, z2.d\n} } } */ +/* { dg-final { scan-assembler { test v96qi 2 z0, z0, z3\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz0, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz1, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz2, \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz6, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz7, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz8, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v48hi 1 z6\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z6.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z7.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z8.d\n} } } */ +/* { dg-final { scan-assembler { test v48hi 2 z6, z6, z2\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz6, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz7, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz8, \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz12, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz13, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz14, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v24si 1 z12\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz15.d, z12.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z13.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z14.d\n} } } */ +/* { dg-final { scan-assembler { test v24si 2 z12, z12, z15\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz12, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz13, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz14, \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz16, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz17, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz18, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v12di 1 z16\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz13.d, z16.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz14.d, z17.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz15.d, z18.d\n} } } */ +/* { dg-final { scan-assembler { test v12di 2 z16, z16, z13\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz16, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz17, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz18, \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz20, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz21, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz22, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v24sf 1 z20\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz23.d, z20.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz24.d, z21.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz25.d, z22.d\n} } } */ +/* { dg-final { scan-assembler { test v24sf 2 z20, z20, z23\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz20, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz21, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz22, \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz26, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz27, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz28, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v12df 1 z26\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz29.d, z26.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz30.d, z27.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz31.d, z28.d\n} } } */ +/* { dg-final { scan-assembler { test v12df 2 z26, z26, z29\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz26, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz27, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz28, \[x0, #5, mul vl\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_move_6.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_move_6.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,129 @@ +/* { dg-do assemble } */ +/* { dg-options "-O -march=armv8-a+sve -msve-vector-bits=256 -mlittle-endian --save-temps" } */ + +typedef char v32qi __attribute__((vector_size(32))); +typedef struct { v32qi a[4]; } v128qi; + +typedef short v16hi __attribute__((vector_size(32))); +typedef struct { v16hi a[4]; } v64hi; + +typedef int v8si __attribute__((vector_size(32))); +typedef struct { v8si a[4]; } v32si; + +typedef long v4di __attribute__((vector_size(32))); +typedef struct { v4di a[4]; } v16di; + +typedef float v8sf __attribute__((vector_size(32))); +typedef struct { v8sf a[4]; } v32sf; + +typedef double v4df __attribute__((vector_size(32))); +typedef struct { v4df a[4]; } v16df; + +#define TEST_TYPE(TYPE, REG1, REG2) \ + void \ + f_##TYPE (TYPE *a) \ + { \ + register TYPE x asm (#REG1) = a[0]; \ + asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \ + register TYPE y asm (#REG2) = x; \ + asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2" \ + : "=&w" (x) : "0" (x), "w" (y)); \ + a[1] = x; \ + } + +TEST_TYPE (v128qi, z0, z4) +TEST_TYPE (v64hi, z6, z2) +TEST_TYPE (v32si, z12, z16) +TEST_TYPE (v16di, z17, z13) +TEST_TYPE (v32sf, z20, z16) +TEST_TYPE (v16df, z24, z28) + +/* { dg-final { scan-assembler {\tldr\tz0, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz1, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz2, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz3, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v128qi 1 z0\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z0.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz5.d, z1.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz6.d, z2.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz7.d, z3.d\n} } } */ +/* { dg-final { scan-assembler { test v128qi 2 z0, z0, z4\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz0, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz1, \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz2, \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz3, \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz6, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz7, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz8, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz9, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v64hi 1 z6\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z6.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z7.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z8.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz5.d, z9.d\n} } } */ +/* { dg-final { scan-assembler { test v64hi 2 z6, z6, z2\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz6, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz7, \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz8, \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz9, \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz12, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz13, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz14, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz15, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v32si 1 z12\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z12.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z13.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz18.d, z14.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz19.d, z15.d\n} } } */ +/* { dg-final { scan-assembler { test v32si 2 z12, z12, z16\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz12, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz13, \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz14, \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz15, \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz17, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz18, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz19, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz20, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16di 1 z17\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz13.d, z17.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz14.d, z18.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz15.d, z19.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z20.d\n} } } */ +/* { dg-final { scan-assembler { test v16di 2 z17, z17, z13\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz17, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz18, \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz19, \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz20, \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz20, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz21, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz22, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz23, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v32sf 1 z20\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z20.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z21.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz18.d, z22.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz19.d, z23.d\n} } } */ +/* { dg-final { scan-assembler { test v32sf 2 z20, z20, z16\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz20, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz21, \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz22, \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz23, \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz24, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz25, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz26, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz27, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16df 1 z24\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz28.d, z24.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz29.d, z25.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz30.d, z26.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz31.d, z27.d\n} } } */ +/* { dg-final { scan-assembler { test v16df 2 z24, z24, z28\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz24, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz25, \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz26, \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz27, \[x0, #7, mul vl\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_1.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_1.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,89 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#ifndef TYPE +#define TYPE unsigned char +#endif + +#ifndef NAME +#define NAME(X) X +#endif + +#define N 1024 + +void __attribute__ ((noinline, noclone)) +NAME(f2) (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c) +{ + for (int i = 0; i < N; ++i) + { + a[i] = c[i * 2]; + b[i] = c[i * 2 + 1]; + } +} + +void __attribute__ ((noinline, noclone)) +NAME(f3) (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d) +{ + for (int i = 0; i < N; ++i) + { + a[i] = d[i * 3]; + b[i] = d[i * 3 + 1]; + c[i] = d[i * 3 + 2]; + } +} + +void __attribute__ ((noinline, noclone)) +NAME(f4) (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d, TYPE *__restrict e) +{ + for (int i = 0; i < N; ++i) + { + a[i] = e[i * 4]; + b[i] = e[i * 4 + 1]; + c[i] = e[i * 4 + 2]; + d[i] = e[i * 4 + 3]; + } +} + +void __attribute__ ((noinline, noclone)) +NAME(g2) (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c) +{ + for (int i = 0; i < N; ++i) + { + c[i * 2] = a[i]; + c[i * 2 + 1] = b[i]; + } +} + +void __attribute__ ((noinline, noclone)) +NAME(g3) (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d) +{ + for (int i = 0; i < N; ++i) + { + d[i * 3] = a[i]; + d[i * 3 + 1] = b[i]; + d[i * 3 + 2] = c[i]; + } +} + +void __attribute__ ((noinline, noclone)) +NAME(g4) (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d, TYPE *__restrict e) +{ + for (int i = 0; i < N; ++i) + { + e[i * 4] = a[i]; + e[i * 4 + 1] = b[i]; + e[i * 4 + 2] = c[i]; + e[i * 4 + 3] = d[i]; + } +} + +/* { dg-final { scan-assembler {\tld2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_1_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_1_run.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,63 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#include "sve_struct_vect_1.c" + +TYPE a[N], b[N], c[N], d[N], e[N * 4]; + +void __attribute__ ((noinline, noclone)) +init_array (TYPE *array, int n, TYPE base, TYPE step) +{ + for (int i = 0; i < n; ++i) + array[i] = base + step * i; +} + +void __attribute__ ((noinline, noclone)) +check_array (TYPE *array, int n, TYPE base, TYPE step) +{ + for (int i = 0; i < n; ++i) + if (array[i] != (TYPE) (base + step * i)) + __builtin_abort (); +} + +int __attribute__ ((optimize (1))) +main (void) +{ + init_array (e, 2 * N, 11, 5); + f2 (a, b, e); + check_array (a, N, 11, 10); + check_array (b, N, 16, 10); + + init_array (e, 3 * N, 7, 6); + f3 (a, b, c, e); + check_array (a, N, 7, 18); + check_array (b, N, 13, 18); + check_array (c, N, 19, 18); + + init_array (e, 4 * N, 4, 11); + f4 (a, b, c, d, e); + check_array (a, N, 4, 44); + check_array (b, N, 15, 44); + check_array (c, N, 26, 44); + check_array (d, N, 37, 44); + + init_array (a, N, 2, 8); + init_array (b, N, 6, 8); + g2 (a, b, e); + check_array (e, 2 * N, 2, 4); + + init_array (a, N, 4, 15); + init_array (b, N, 9, 15); + init_array (c, N, 14, 15); + g3 (a, b, c, e); + check_array (e, 3 * N, 4, 5); + + init_array (a, N, 14, 36); + init_array (b, N, 23, 36); + init_array (c, N, 32, 36); + init_array (d, N, 41, 36); + g4 (a, b, c, d, e); + check_array (e, 4 * N, 14, 9); + + return 0; +} Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_2.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_2.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,12 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned short +#include "sve_struct_vect_1.c" + +/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_2_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_2_run.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,5 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned short +#include "sve_struct_vect_1_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_3.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_3.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,12 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned int +#include "sve_struct_vect_1.c" + +/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_3_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_3_run.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,5 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned int +#include "sve_struct_vect_1_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_4.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_4.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,12 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned long +#include "sve_struct_vect_1.c" + +/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_4_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_4_run.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,5 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned long +#include "sve_struct_vect_1_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_5.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_5.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,12 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE float +#include "sve_struct_vect_1.c" + +/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_5_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_5_run.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,5 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE float +#include "sve_struct_vect_1_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_6.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_6.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,12 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE double +#include "sve_struct_vect_1.c" + +/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_6_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_6_run.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,5 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE double +#include "sve_struct_vect_1_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_7.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_7.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,84 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#ifndef TYPE +#define TYPE unsigned char +#define ITYPE signed char +#endif + +void __attribute__ ((noinline, noclone)) +f2 (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, ITYPE n) +{ + for (ITYPE i = 0; i < n; ++i) + { + a[i] = c[i * 2]; + b[i] = c[i * 2 + 1]; + } +} + +void __attribute__ ((noinline, noclone)) +f3 (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d, ITYPE n) +{ + for (ITYPE i = 0; i < n; ++i) + { + a[i] = d[i * 3]; + b[i] = d[i * 3 + 1]; + c[i] = d[i * 3 + 2]; + } +} + +void __attribute__ ((noinline, noclone)) +f4 (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d, TYPE *__restrict e, ITYPE n) +{ + for (ITYPE i = 0; i < n; ++i) + { + a[i] = e[i * 4]; + b[i] = e[i * 4 + 1]; + c[i] = e[i * 4 + 2]; + d[i] = e[i * 4 + 3]; + } +} + +void __attribute__ ((noinline, noclone)) +g2 (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, ITYPE n) +{ + for (ITYPE i = 0; i < n; ++i) + { + c[i * 2] = a[i]; + c[i * 2 + 1] = b[i]; + } +} + +void __attribute__ ((noinline, noclone)) +g3 (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d, ITYPE n) +{ + for (ITYPE i = 0; i < n; ++i) + { + d[i * 3] = a[i]; + d[i * 3 + 1] = b[i]; + d[i * 3 + 2] = c[i]; + } +} + +void __attribute__ ((noinline, noclone)) +g4 (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d, TYPE *__restrict e, ITYPE n) +{ + for (ITYPE i = 0; i < n; ++i) + { + e[i * 4] = a[i]; + e[i * 4 + 1] = b[i]; + e[i * 4 + 2] = c[i]; + e[i * 4 + 3] = d[i]; + } +} + +/* { dg-final { scan-assembler {\tld2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_7_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_7_run.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,65 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#include "sve_struct_vect_7.c" + +#define N 93 + +TYPE a[N], b[N], c[N], d[N], e[N * 4]; + +void __attribute__ ((noinline, noclone)) +init_array (TYPE *array, int n, TYPE base, TYPE step) +{ + for (int i = 0; i < n; ++i) + array[i] = base + step * i; +} + +void __attribute__ ((noinline, noclone)) +check_array (TYPE *array, int n, TYPE base, TYPE step) +{ + for (int i = 0; i < n; ++i) + if (array[i] != (TYPE) (base + step * i)) + __builtin_abort (); +} + +int __attribute__ ((optimize (1))) +main (void) +{ + init_array (e, 2 * N, 11, 5); + f2 (a, b, e, N); + check_array (a, N, 11, 10); + check_array (b, N, 16, 10); + + init_array (e, 3 * N, 7, 6); + f3 (a, b, c, e, N); + check_array (a, N, 7, 18); + check_array (b, N, 13, 18); + check_array (c, N, 19, 18); + + init_array (e, 4 * N, 4, 11); + f4 (a, b, c, d, e, N); + check_array (a, N, 4, 44); + check_array (b, N, 15, 44); + check_array (c, N, 26, 44); + check_array (d, N, 37, 44); + + init_array (a, N, 2, 8); + init_array (b, N, 6, 8); + g2 (a, b, e, N); + check_array (e, 2 * N, 2, 4); + + init_array (a, N, 4, 15); + init_array (b, N, 9, 15); + init_array (c, N, 14, 15); + g3 (a, b, c, e, N); + check_array (e, 3 * N, 4, 5); + + init_array (a, N, 14, 36); + init_array (b, N, 23, 36); + init_array (c, N, 32, 36); + init_array (d, N, 41, 36); + g4 (a, b, c, d, e, N); + check_array (e, 4 * N, 14, 9); + + return 0; +} Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_8.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_8.c 2017-11-08 15:06:27.251849138 +0000 @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned short +#define ITYPE short +#include "sve_struct_vect_7.c" + +/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_8_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_8_run.c 2017-11-08 15:06:27.251849138 +0000 @@ -0,0 +1,6 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned short +#define ITYPE short +#include "sve_struct_vect_7_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_9.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_9.c 2017-11-08 15:06:27.251849138 +0000 @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned int +#define ITYPE int +#include "sve_struct_vect_7.c" + +/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_9_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_9_run.c 2017-11-08 15:06:27.251849138 +0000 @@ -0,0 +1,6 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned int +#define ITYPE int +#include "sve_struct_vect_7_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_10.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_10.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned long +#define ITYPE long +#include "sve_struct_vect_7.c" + +/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_10_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_10_run.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,6 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned long +#define ITYPE long +#include "sve_struct_vect_7_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_11.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_11.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE _Float16 +#define ITYPE short +#include "sve_struct_vect_7.c" + +/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_11_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_11_run.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,6 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE _Float16 +#define ITYPE short +#include "sve_struct_vect_7_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_12.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_12.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE float +#define ITYPE int +#include "sve_struct_vect_7.c" + +/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_12_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_12_run.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,6 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE float +#define ITYPE int +#include "sve_struct_vect_7_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_13.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_13.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE double +#define ITYPE long +#include "sve_struct_vect_7.c" + +/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_13_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_13_run.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,6 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE double +#define ITYPE long +#include "sve_struct_vect_7_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_14.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_14.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,72 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve -msve-vector-bits=256 --save-temps" } */ + +#define TYPE unsigned char +#define NAME(X) qi_##X +#include "sve_struct_vect_1.c" +#undef NAME +#undef TYPE + +#define TYPE unsigned short +#define NAME(X) hi_##X +#include "sve_struct_vect_1.c" +#undef NAME +#undef TYPE + +#define TYPE unsigned int +#define NAME(X) si_##X +#include "sve_struct_vect_1.c" +#undef NAME +#undef TYPE + +#define TYPE unsigned long +#define NAME(X) di_##X +#include "sve_struct_vect_1.c" +#undef NAME +#undef TYPE + +#define TYPE _Float16 +#define NAME(X) hf_##X +#include "sve_struct_vect_1.c" +#undef NAME +#undef TYPE + +#define TYPE float +#define NAME(X) sf_##X +#include "sve_struct_vect_1.c" +#undef NAME +#undef TYPE + +#define TYPE double +#define NAME(X) df_##X +#include "sve_struct_vect_1.c" +#undef NAME +#undef TYPE + +/* { dg-final { scan-assembler-times {\tld2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tld2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_15.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_15.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,32 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve -msve-vector-bits=512 --save-temps" } */ + +#include "sve_struct_vect_14.c" + +/* { dg-final { scan-assembler-times {\tld2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tld2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_16.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_16.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,32 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve -msve-vector-bits=1024 --save-temps" } */ + +#include "sve_struct_vect_14.c" + +/* { dg-final { scan-assembler-times {\tld2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tld2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_17.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_17.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,32 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve -msve-vector-bits=2048 --save-temps" } */ + +#include "sve_struct_vect_14.c" + +/* { dg-final { scan-assembler-times {\tld2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tld2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */
Index: gcc/testsuite/gcc.target/aarch64/sve_struct_move_1.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_move_1.c 2017-11-08 15:06:27.247849138 +0000 @@ -0,0 +1,129 @@ +/* { dg-do assemble } */ +/* { dg-options "-O -march=armv8-a+sve -msve-vector-bits=256 -mbig-endian --save-temps" } */ + +typedef char v32qi __attribute__((vector_size(32))); +typedef struct { v32qi a[2]; } v64qi; + +typedef short v16hi __attribute__((vector_size(32))); +typedef struct { v16hi a[2]; } v32hi; + +typedef int v8si __attribute__((vector_size(32))); +typedef struct { v8si a[2]; } v16si; + +typedef long v4di __attribute__((vector_size(32))); +typedef struct { v4di a[2]; } v8di; + +typedef _Float16 v16hf __attribute__((vector_size(32))); +typedef struct { v16hf a[2]; } v32hf; + +typedef float v8sf __attribute__((vector_size(32))); +typedef struct { v8sf a[2]; } v16sf; + +typedef double v4df __attribute__((vector_size(32))); +typedef struct { v4df a[2]; } v8df; + +#define TEST_TYPE(TYPE, REG1, REG2) \ + void \ + f1_##TYPE (TYPE *a) \ + { \ + register TYPE x asm (#REG1) = a[0]; \ + asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \ + register TYPE y asm (#REG2) = x; \ + asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2" \ + : "=&w" (x) : "0" (x), "w" (y)); \ + a[1] = x; \ + } \ + /* This must compile, but we don't care how. */ \ + void \ + f2_##TYPE (TYPE *a) \ + { \ + TYPE x = a[0]; \ + x.a[0][3] = 1; \ + x.a[1][2] = 12; \ + asm volatile ("# %0" :: "w" (x)); \ + } \ + void \ + f3_##TYPE (TYPE *a, int i) \ + { \ + TYPE x = a[0]; \ + x.a[0][i] = 1; \ + asm volatile ("# %0" :: "w" (x)); \ + } \ + void \ + f4_##TYPE (TYPE *a, int i, int j) \ + { \ + TYPE x = a[0]; \ + x.a[i][j] = 44; \ + asm volatile ("# %0" :: "w" (x)); \ + } + +TEST_TYPE (v64qi, z0, z2) +TEST_TYPE (v32hi, z5, z7) +TEST_TYPE (v16si, z10, z12) +TEST_TYPE (v8di, z15, z17) +TEST_TYPE (v32hf, z18, z20) +TEST_TYPE (v16sf, z21, z23) +TEST_TYPE (v8df, z28, z30) + +/* { dg-final { scan-assembler {\tld1b\tz0.b, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1b\tz1.b, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v64qi 1 z0\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z0.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z1.d\n} } } */ +/* { dg-final { scan-assembler { test v64qi 2 z0, z0, z2\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz0.b, p[0-7], \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz1.b, p[0-7], \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1h\tz5.h, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz6.h, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v32hi 1 z5\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz7.d, z5.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz8.d, z6.d\n} } } */ +/* { dg-final { scan-assembler { test v32hi 2 z5, z5, z7\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz5.h, p[0-7], \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz6.h, p[0-7], \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1w\tz10.s, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz11.s, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16si 1 z10\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz12.d, z10.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz13.d, z11.d\n} } } */ +/* { dg-final { scan-assembler { test v16si 2 z10, z10, z12\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz10.s, p[0-7], \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz11.s, p[0-7], \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1d\tz15.d, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz16.d, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v8di 1 z15\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z15.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz18.d, z16.d\n} } } */ +/* { dg-final { scan-assembler { test v8di 2 z15, z15, z17\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz15.d, p[0-7], \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz16.d, p[0-7], \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1h\tz18.h, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz19.h, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v32hf 1 z18\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz20.d, z18.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz21.d, z19.d\n} } } */ +/* { dg-final { scan-assembler { test v32hf 2 z18, z18, z20\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz18.h, p[0-7], \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz19.h, p[0-7], \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1w\tz21.s, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz22.s, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16sf 1 z21\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz23.d, z21.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz24.d, z22.d\n} } } */ +/* { dg-final { scan-assembler { test v16sf 2 z21, z21, z23\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz21.s, p[0-7], \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz22.s, p[0-7], \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1d\tz28.d, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz29.d, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v8df 1 z28\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz30.d, z28.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz31.d, z29.d\n} } } */ +/* { dg-final { scan-assembler { test v8df 2 z28, z28, z30\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz28.d, p[0-7], \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz29.d, p[0-7], \[x0, #3, mul vl\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_move_2.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_move_2.c 2017-11-08 15:06:27.247849138 +0000 @@ -0,0 +1,127 @@ +/* { dg-do assemble } */ +/* { dg-options "-O -march=armv8-a+sve -msve-vector-bits=256 -mbig-endian --save-temps" } */ + +typedef char v32qi __attribute__((vector_size(32))); +typedef struct { v32qi a[3]; } v96qi; + +typedef short v16hi __attribute__((vector_size(32))); +typedef struct { v16hi a[3]; } v48hi; + +typedef int v8si __attribute__((vector_size(32))); +typedef struct { v8si a[3]; } v24si; + +typedef long v4di __attribute__((vector_size(32))); +typedef struct { v4di a[3]; } v12di; + +typedef _Float16 v16hf __attribute__((vector_size(32))); +typedef struct { v16hf a[3]; } v48hf; + +typedef float v8sf __attribute__((vector_size(32))); +typedef struct { v8sf a[3]; } v24sf; + +typedef double v4df __attribute__((vector_size(32))); +typedef struct { v4df a[3]; } v12df; + +#define TEST_TYPE(TYPE, REG1, REG2) \ + void \ + f_##TYPE (TYPE *a) \ + { \ + register TYPE x asm (#REG1) = a[0]; \ + asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \ + register TYPE y asm (#REG2) = x; \ + asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2" \ + : "=&w" (x) : "0" (x), "w" (y)); \ + a[1] = x; \ + } + +TEST_TYPE (v96qi, z0, z3) +TEST_TYPE (v48hi, z6, z2) +TEST_TYPE (v24si, z12, z15) +TEST_TYPE (v12di, z16, z13) +TEST_TYPE (v48hf, z18, z1) +TEST_TYPE (v24sf, z20, z23) +TEST_TYPE (v12df, z26, z29) + +/* { dg-final { scan-assembler {\tld1b\tz0.b, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1b\tz1.b, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1b\tz2.b, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v96qi 1 z0\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z0.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z1.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz5.d, z2.d\n} } } */ +/* { dg-final { scan-assembler { test v96qi 2 z0, z0, z3\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz0.b, p[0-7], \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz1.b, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz2.b, p[0-7], \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1h\tz6.h, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz7.h, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz8.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v48hi 1 z6\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z6.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z7.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z8.d\n} } } */ +/* { dg-final { scan-assembler { test v48hi 2 z6, z6, z2\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz6.h, p[0-7], \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz7.h, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz8.h, p[0-7], \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1w\tz12.s, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz13.s, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz14.s, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v24si 1 z12\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz15.d, z12.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z13.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z14.d\n} } } */ +/* { dg-final { scan-assembler { test v24si 2 z12, z12, z15\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz12.s, p[0-7], \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz13.s, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz14.s, p[0-7], \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1d\tz16.d, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz17.d, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz18.d, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v12di 1 z16\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz13.d, z16.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz14.d, z17.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz15.d, z18.d\n} } } */ +/* { dg-final { scan-assembler { test v12di 2 z16, z16, z13\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz16.d, p[0-7], \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz17.d, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz18.d, p[0-7], \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1h\tz18.h, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz19.h, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz20.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v48hf 1 z18\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz1.d, z18.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z19.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z20.d\n} } } */ +/* { dg-final { scan-assembler { test v48hf 2 z18, z18, z1\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz18.h, p[0-7], \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz19.h, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz20.h, p[0-7], \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1w\tz20.s, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz21.s, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz22.s, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v24sf 1 z20\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz23.d, z20.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz24.d, z21.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz25.d, z22.d\n} } } */ +/* { dg-final { scan-assembler { test v24sf 2 z20, z20, z23\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz20.s, p[0-7], \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz21.s, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz22.s, p[0-7], \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1d\tz26.d, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz27.d, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz28.d, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v12df 1 z26\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz29.d, z26.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz30.d, z27.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz31.d, z28.d\n} } } */ +/* { dg-final { scan-assembler { test v12df 2 z26, z26, z29\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz26.d, p[0-7], \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz27.d, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz28.d, p[0-7], \[x0, #5, mul vl\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_move_3.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_move_3.c 2017-11-08 15:06:27.247849138 +0000 @@ -0,0 +1,148 @@ +/* { dg-do assemble } */ +/* { dg-options "-O -march=armv8-a+sve -msve-vector-bits=256 -mbig-endian --save-temps" } */ + +typedef char v32qi __attribute__((vector_size(32))); +typedef struct { v32qi a[4]; } v128qi; + +typedef short v16hi __attribute__((vector_size(32))); +typedef struct { v16hi a[4]; } v64hi; + +typedef int v8si __attribute__((vector_size(32))); +typedef struct { v8si a[4]; } v32si; + +typedef long v4di __attribute__((vector_size(32))); +typedef struct { v4di a[4]; } v16di; + +typedef _Float16 v16hf __attribute__((vector_size(32))); +typedef struct { v16hf a[4]; } v64hf; + +typedef float v8sf __attribute__((vector_size(32))); +typedef struct { v8sf a[4]; } v32sf; + +typedef double v4df __attribute__((vector_size(32))); +typedef struct { v4df a[4]; } v16df; + +#define TEST_TYPE(TYPE, REG1, REG2) \ + void \ + f_##TYPE (TYPE *a) \ + { \ + register TYPE x asm (#REG1) = a[0]; \ + asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \ + register TYPE y asm (#REG2) = x; \ + asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2" \ + : "=&w" (x) : "0" (x), "w" (y)); \ + a[1] = x; \ + } + +TEST_TYPE (v128qi, z0, z4) +TEST_TYPE (v64hi, z6, z2) +TEST_TYPE (v32si, z12, z16) +TEST_TYPE (v16di, z17, z13) +TEST_TYPE (v64hf, z18, z1) +TEST_TYPE (v32sf, z20, z16) +TEST_TYPE (v16df, z24, z28) + +/* { dg-final { scan-assembler {\tld1b\tz0.b, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1b\tz1.b, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1b\tz2.b, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1b\tz3.b, p[0-7]/z, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v128qi 1 z0\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z0.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz5.d, z1.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz6.d, z2.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz7.d, z3.d\n} } } */ +/* { dg-final { scan-assembler { test v128qi 2 z0, z0, z4\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz0.b, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz1.b, p[0-7], \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz2.b, p[0-7], \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1b\tz3.b, p[0-7], \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1h\tz6.h, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz7.h, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz8.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz9.h, p[0-7]/z, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v64hi 1 z6\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z6.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z7.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z8.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz5.d, z9.d\n} } } */ +/* { dg-final { scan-assembler { test v64hi 2 z6, z6, z2\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz6.h, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz7.h, p[0-7], \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz8.h, p[0-7], \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz9.h, p[0-7], \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1w\tz12.s, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz13.s, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz14.s, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz15.s, p[0-7]/z, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v32si 1 z12\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z12.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z13.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz18.d, z14.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz19.d, z15.d\n} } } */ +/* { dg-final { scan-assembler { test v32si 2 z12, z12, z16\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz12.s, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz13.s, p[0-7], \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz14.s, p[0-7], \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz15.s, p[0-7], \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1d\tz17.d, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz18.d, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz19.d, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz20.d, p[0-7]/z, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16di 1 z17\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz13.d, z17.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz14.d, z18.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz15.d, z19.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z20.d\n} } } */ +/* { dg-final { scan-assembler { test v16di 2 z17, z17, z13\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz17.d, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz18.d, p[0-7], \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz19.d, p[0-7], \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz20.d, p[0-7], \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1h\tz18.h, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz19.h, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz20.h, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1h\tz21.h, p[0-7]/z, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v64hf 1 z18\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz1.d, z18.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z19.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z20.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z21.d\n} } } */ +/* { dg-final { scan-assembler { test v64hf 2 z18, z18, z1\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz18.h, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz19.h, p[0-7], \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz20.h, p[0-7], \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1h\tz21.h, p[0-7], \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1w\tz20.s, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz21.s, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz22.s, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1w\tz23.s, p[0-7]/z, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v32sf 1 z20\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z20.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z21.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz18.d, z22.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz19.d, z23.d\n} } } */ +/* { dg-final { scan-assembler { test v32sf 2 z20, z20, z16\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz20.s, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz21.s, p[0-7], \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz22.s, p[0-7], \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1w\tz23.s, p[0-7], \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tld1d\tz24.d, p[0-7]/z, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz25.d, p[0-7]/z, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz26.d, p[0-7]/z, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tld1d\tz27.d, p[0-7]/z, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16df 1 z24\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz28.d, z24.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz29.d, z25.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz30.d, z26.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz31.d, z27.d\n} } } */ +/* { dg-final { scan-assembler { test v16df 2 z24, z24, z28\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz24.d, p[0-7], \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz25.d, p[0-7], \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz26.d, p[0-7], \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tst1d\tz27.d, p[0-7], \[x0, #7, mul vl\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_move_4.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_move_4.c 2017-11-08 15:06:27.247849138 +0000 @@ -0,0 +1,116 @@ +/* { dg-do assemble } */ +/* { dg-options "-O -march=armv8-a+sve -msve-vector-bits=256 -mlittle-endian --save-temps" } */ + +typedef char v32qi __attribute__((vector_size(32))); +typedef struct { v32qi a[2]; } v64qi; + +typedef short v16hi __attribute__((vector_size(32))); +typedef struct { v16hi a[2]; } v32hi; + +typedef int v8si __attribute__((vector_size(32))); +typedef struct { v8si a[2]; } v16si; + +typedef long v4di __attribute__((vector_size(32))); +typedef struct { v4di a[2]; } v8di; + +typedef float v8sf __attribute__((vector_size(32))); +typedef struct { v8sf a[2]; } v16sf; + +typedef double v4df __attribute__((vector_size(32))); +typedef struct { v4df a[2]; } v8df; + +#define TEST_TYPE(TYPE, REG1, REG2) \ + void \ + f1_##TYPE (TYPE *a) \ + { \ + register TYPE x asm (#REG1) = a[0]; \ + asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \ + register TYPE y asm (#REG2) = x; \ + asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2" \ + : "=&w" (x) : "0" (x), "w" (y)); \ + a[1] = x; \ + } \ + /* This must compile, but we don't care how. */ \ + void \ + f2_##TYPE (TYPE *a) \ + { \ + TYPE x = a[0]; \ + x.a[0][3] = 1; \ + x.a[1][2] = 12; \ + asm volatile ("# %0" :: "w" (x)); \ + } \ + void \ + f3_##TYPE (TYPE *a, int i) \ + { \ + TYPE x = a[0]; \ + x.a[0][i] = 1; \ + asm volatile ("# %0" :: "w" (x)); \ + } \ + void \ + f4_##TYPE (TYPE *a, int i, int j) \ + { \ + TYPE x = a[0]; \ + x.a[i][j] = 44; \ + asm volatile ("# %0" :: "w" (x)); \ + } + +TEST_TYPE (v64qi, z0, z2) +TEST_TYPE (v32hi, z5, z7) +TEST_TYPE (v16si, z10, z12) +TEST_TYPE (v8di, z15, z17) +TEST_TYPE (v16sf, z20, z23) +TEST_TYPE (v8df, z28, z30) + +/* { dg-final { scan-assembler {\tldr\tz0, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz1, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v64qi 1 z0\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z0.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z1.d\n} } } */ +/* { dg-final { scan-assembler { test v64qi 2 z0, z0, z2\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz0, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz1, \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz5, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz6, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v32hi 1 z5\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz7.d, z5.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz8.d, z6.d\n} } } */ +/* { dg-final { scan-assembler { test v32hi 2 z5, z5, z7\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz5, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz6, \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz10, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz11, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16si 1 z10\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz12.d, z10.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz13.d, z11.d\n} } } */ +/* { dg-final { scan-assembler { test v16si 2 z10, z10, z12\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz10, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz11, \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz15, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz16, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v8di 1 z15\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z15.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz18.d, z16.d\n} } } */ +/* { dg-final { scan-assembler { test v8di 2 z15, z15, z17\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz15, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz16, \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz20, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz21, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16sf 1 z20\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz23.d, z20.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz24.d, z21.d\n} } } */ +/* { dg-final { scan-assembler { test v16sf 2 z20, z20, z23\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz20, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz21, \[x0, #3, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz28, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz29, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v8df 1 z28\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz30.d, z28.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz31.d, z29.d\n} } } */ +/* { dg-final { scan-assembler { test v8df 2 z28, z28, z30\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz28, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz29, \[x0, #3, mul vl\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_move_5.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_move_5.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,111 @@ +/* { dg-do assemble } */ +/* { dg-options "-O -march=armv8-a+sve -msve-vector-bits=256 -mlittle-endian --save-temps" } */ + +typedef char v32qi __attribute__((vector_size(32))); +typedef struct { v32qi a[3]; } v96qi; + +typedef short v16hi __attribute__((vector_size(32))); +typedef struct { v16hi a[3]; } v48hi; + +typedef int v8si __attribute__((vector_size(32))); +typedef struct { v8si a[3]; } v24si; + +typedef long v4di __attribute__((vector_size(32))); +typedef struct { v4di a[3]; } v12di; + +typedef float v8sf __attribute__((vector_size(32))); +typedef struct { v8sf a[3]; } v24sf; + +typedef double v4df __attribute__((vector_size(32))); +typedef struct { v4df a[3]; } v12df; + +#define TEST_TYPE(TYPE, REG1, REG2) \ + void \ + f_##TYPE (TYPE *a) \ + { \ + register TYPE x asm (#REG1) = a[0]; \ + asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \ + register TYPE y asm (#REG2) = x; \ + asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2" \ + : "=&w" (x) : "0" (x), "w" (y)); \ + a[1] = x; \ + } + +TEST_TYPE (v96qi, z0, z3) +TEST_TYPE (v48hi, z6, z2) +TEST_TYPE (v24si, z12, z15) +TEST_TYPE (v12di, z16, z13) +TEST_TYPE (v24sf, z20, z23) +TEST_TYPE (v12df, z26, z29) + +/* { dg-final { scan-assembler {\tldr\tz0, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz1, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz2, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v96qi 1 z0\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z0.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z1.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz5.d, z2.d\n} } } */ +/* { dg-final { scan-assembler { test v96qi 2 z0, z0, z3\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz0, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz1, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz2, \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz6, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz7, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz8, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v48hi 1 z6\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z6.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z7.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z8.d\n} } } */ +/* { dg-final { scan-assembler { test v48hi 2 z6, z6, z2\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz6, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz7, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz8, \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz12, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz13, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz14, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v24si 1 z12\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz15.d, z12.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z13.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z14.d\n} } } */ +/* { dg-final { scan-assembler { test v24si 2 z12, z12, z15\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz12, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz13, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz14, \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz16, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz17, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz18, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v12di 1 z16\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz13.d, z16.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz14.d, z17.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz15.d, z18.d\n} } } */ +/* { dg-final { scan-assembler { test v12di 2 z16, z16, z13\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz16, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz17, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz18, \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz20, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz21, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz22, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v24sf 1 z20\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz23.d, z20.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz24.d, z21.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz25.d, z22.d\n} } } */ +/* { dg-final { scan-assembler { test v24sf 2 z20, z20, z23\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz20, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz21, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz22, \[x0, #5, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz26, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz27, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz28, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v12df 1 z26\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz29.d, z26.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz30.d, z27.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz31.d, z28.d\n} } } */ +/* { dg-final { scan-assembler { test v12df 2 z26, z26, z29\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz26, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz27, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz28, \[x0, #5, mul vl\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_move_6.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_move_6.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,129 @@ +/* { dg-do assemble } */ +/* { dg-options "-O -march=armv8-a+sve -msve-vector-bits=256 -mlittle-endian --save-temps" } */ + +typedef char v32qi __attribute__((vector_size(32))); +typedef struct { v32qi a[4]; } v128qi; + +typedef short v16hi __attribute__((vector_size(32))); +typedef struct { v16hi a[4]; } v64hi; + +typedef int v8si __attribute__((vector_size(32))); +typedef struct { v8si a[4]; } v32si; + +typedef long v4di __attribute__((vector_size(32))); +typedef struct { v4di a[4]; } v16di; + +typedef float v8sf __attribute__((vector_size(32))); +typedef struct { v8sf a[4]; } v32sf; + +typedef double v4df __attribute__((vector_size(32))); +typedef struct { v4df a[4]; } v16df; + +#define TEST_TYPE(TYPE, REG1, REG2) \ + void \ + f_##TYPE (TYPE *a) \ + { \ + register TYPE x asm (#REG1) = a[0]; \ + asm volatile ("# test " #TYPE " 1 %S0" :: "w" (x)); \ + register TYPE y asm (#REG2) = x; \ + asm volatile ("# test " #TYPE " 2 %S0, %S1, %S2" \ + : "=&w" (x) : "0" (x), "w" (y)); \ + a[1] = x; \ + } + +TEST_TYPE (v128qi, z0, z4) +TEST_TYPE (v64hi, z6, z2) +TEST_TYPE (v32si, z12, z16) +TEST_TYPE (v16di, z17, z13) +TEST_TYPE (v32sf, z20, z16) +TEST_TYPE (v16df, z24, z28) + +/* { dg-final { scan-assembler {\tldr\tz0, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz1, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz2, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz3, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v128qi 1 z0\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z0.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz5.d, z1.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz6.d, z2.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz7.d, z3.d\n} } } */ +/* { dg-final { scan-assembler { test v128qi 2 z0, z0, z4\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz0, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz1, \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz2, \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz3, \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz6, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz7, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz8, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz9, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v64hi 1 z6\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz2.d, z6.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz3.d, z7.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz4.d, z8.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz5.d, z9.d\n} } } */ +/* { dg-final { scan-assembler { test v64hi 2 z6, z6, z2\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz6, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz7, \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz8, \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz9, \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz12, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz13, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz14, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz15, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v32si 1 z12\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z12.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z13.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz18.d, z14.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz19.d, z15.d\n} } } */ +/* { dg-final { scan-assembler { test v32si 2 z12, z12, z16\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz12, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz13, \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz14, \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz15, \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz17, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz18, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz19, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz20, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16di 1 z17\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz13.d, z17.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz14.d, z18.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz15.d, z19.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z20.d\n} } } */ +/* { dg-final { scan-assembler { test v16di 2 z17, z17, z13\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz17, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz18, \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz19, \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz20, \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz20, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz21, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz22, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz23, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v32sf 1 z20\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz16.d, z20.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz17.d, z21.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz18.d, z22.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz19.d, z23.d\n} } } */ +/* { dg-final { scan-assembler { test v32sf 2 z20, z20, z16\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz20, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz21, \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz22, \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz23, \[x0, #7, mul vl\]\n} } } */ + +/* { dg-final { scan-assembler {\tldr\tz24, \[x0\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz25, \[x0, #1, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz26, \[x0, #2, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tldr\tz27, \[x0, #3, mul vl\]\n} } } */ +/* { dg-final { scan-assembler { test v16df 1 z24\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz28.d, z24.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz29.d, z25.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz30.d, z26.d\n} } } */ +/* { dg-final { scan-assembler {\tmov\tz31.d, z27.d\n} } } */ +/* { dg-final { scan-assembler { test v16df 2 z24, z24, z28\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz24, \[x0, #4, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz25, \[x0, #5, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz26, \[x0, #6, mul vl\]\n} } } */ +/* { dg-final { scan-assembler {\tstr\tz27, \[x0, #7, mul vl\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_1.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_1.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,89 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#ifndef TYPE +#define TYPE unsigned char +#endif + +#ifndef NAME +#define NAME(X) X +#endif + +#define N 1024 + +void __attribute__ ((noinline, noclone)) +NAME(f2) (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c) +{ + for (int i = 0; i < N; ++i) + { + a[i] = c[i * 2]; + b[i] = c[i * 2 + 1]; + } +} + +void __attribute__ ((noinline, noclone)) +NAME(f3) (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d) +{ + for (int i = 0; i < N; ++i) + { + a[i] = d[i * 3]; + b[i] = d[i * 3 + 1]; + c[i] = d[i * 3 + 2]; + } +} + +void __attribute__ ((noinline, noclone)) +NAME(f4) (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d, TYPE *__restrict e) +{ + for (int i = 0; i < N; ++i) + { + a[i] = e[i * 4]; + b[i] = e[i * 4 + 1]; + c[i] = e[i * 4 + 2]; + d[i] = e[i * 4 + 3]; + } +} + +void __attribute__ ((noinline, noclone)) +NAME(g2) (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c) +{ + for (int i = 0; i < N; ++i) + { + c[i * 2] = a[i]; + c[i * 2 + 1] = b[i]; + } +} + +void __attribute__ ((noinline, noclone)) +NAME(g3) (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d) +{ + for (int i = 0; i < N; ++i) + { + d[i * 3] = a[i]; + d[i * 3 + 1] = b[i]; + d[i * 3 + 2] = c[i]; + } +} + +void __attribute__ ((noinline, noclone)) +NAME(g4) (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d, TYPE *__restrict e) +{ + for (int i = 0; i < N; ++i) + { + e[i * 4] = a[i]; + e[i * 4 + 1] = b[i]; + e[i * 4 + 2] = c[i]; + e[i * 4 + 3] = d[i]; + } +} + +/* { dg-final { scan-assembler {\tld2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_1_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_1_run.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,63 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#include "sve_struct_vect_1.c" + +TYPE a[N], b[N], c[N], d[N], e[N * 4]; + +void __attribute__ ((noinline, noclone)) +init_array (TYPE *array, int n, TYPE base, TYPE step) +{ + for (int i = 0; i < n; ++i) + array[i] = base + step * i; +} + +void __attribute__ ((noinline, noclone)) +check_array (TYPE *array, int n, TYPE base, TYPE step) +{ + for (int i = 0; i < n; ++i) + if (array[i] != (TYPE) (base + step * i)) + __builtin_abort (); +} + +int __attribute__ ((optimize (1))) +main (void) +{ + init_array (e, 2 * N, 11, 5); + f2 (a, b, e); + check_array (a, N, 11, 10); + check_array (b, N, 16, 10); + + init_array (e, 3 * N, 7, 6); + f3 (a, b, c, e); + check_array (a, N, 7, 18); + check_array (b, N, 13, 18); + check_array (c, N, 19, 18); + + init_array (e, 4 * N, 4, 11); + f4 (a, b, c, d, e); + check_array (a, N, 4, 44); + check_array (b, N, 15, 44); + check_array (c, N, 26, 44); + check_array (d, N, 37, 44); + + init_array (a, N, 2, 8); + init_array (b, N, 6, 8); + g2 (a, b, e); + check_array (e, 2 * N, 2, 4); + + init_array (a, N, 4, 15); + init_array (b, N, 9, 15); + init_array (c, N, 14, 15); + g3 (a, b, c, e); + check_array (e, 3 * N, 4, 5); + + init_array (a, N, 14, 36); + init_array (b, N, 23, 36); + init_array (c, N, 32, 36); + init_array (d, N, 41, 36); + g4 (a, b, c, d, e); + check_array (e, 4 * N, 14, 9); + + return 0; +} Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_2.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_2.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,12 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned short +#include "sve_struct_vect_1.c" + +/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_2_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_2_run.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,5 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned short +#include "sve_struct_vect_1_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_3.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_3.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,12 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned int +#include "sve_struct_vect_1.c" + +/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_3_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_3_run.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,5 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned int +#include "sve_struct_vect_1_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_4.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_4.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,12 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned long +#include "sve_struct_vect_1.c" + +/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_4_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_4_run.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,5 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned long +#include "sve_struct_vect_1_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_5.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_5.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,12 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE float +#include "sve_struct_vect_1.c" + +/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_5_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_5_run.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,5 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE float +#include "sve_struct_vect_1_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_6.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_6.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,12 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE double +#include "sve_struct_vect_1.c" + +/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_6_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_6_run.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,5 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE double +#include "sve_struct_vect_1_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_7.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_7.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,84 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#ifndef TYPE +#define TYPE unsigned char +#define ITYPE signed char +#endif + +void __attribute__ ((noinline, noclone)) +f2 (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, ITYPE n) +{ + for (ITYPE i = 0; i < n; ++i) + { + a[i] = c[i * 2]; + b[i] = c[i * 2 + 1]; + } +} + +void __attribute__ ((noinline, noclone)) +f3 (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d, ITYPE n) +{ + for (ITYPE i = 0; i < n; ++i) + { + a[i] = d[i * 3]; + b[i] = d[i * 3 + 1]; + c[i] = d[i * 3 + 2]; + } +} + +void __attribute__ ((noinline, noclone)) +f4 (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d, TYPE *__restrict e, ITYPE n) +{ + for (ITYPE i = 0; i < n; ++i) + { + a[i] = e[i * 4]; + b[i] = e[i * 4 + 1]; + c[i] = e[i * 4 + 2]; + d[i] = e[i * 4 + 3]; + } +} + +void __attribute__ ((noinline, noclone)) +g2 (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, ITYPE n) +{ + for (ITYPE i = 0; i < n; ++i) + { + c[i * 2] = a[i]; + c[i * 2 + 1] = b[i]; + } +} + +void __attribute__ ((noinline, noclone)) +g3 (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d, ITYPE n) +{ + for (ITYPE i = 0; i < n; ++i) + { + d[i * 3] = a[i]; + d[i * 3 + 1] = b[i]; + d[i * 3 + 2] = c[i]; + } +} + +void __attribute__ ((noinline, noclone)) +g4 (TYPE *__restrict a, TYPE *__restrict b, TYPE *__restrict c, + TYPE *__restrict d, TYPE *__restrict e, ITYPE n) +{ + for (ITYPE i = 0; i < n; ++i) + { + e[i * 4] = a[i]; + e[i * 4 + 1] = b[i]; + e[i * 4 + 2] = c[i]; + e[i * 4 + 3] = d[i]; + } +} + +/* { dg-final { scan-assembler {\tld2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_7_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_7_run.c 2017-11-08 15:06:27.250849138 +0000 @@ -0,0 +1,65 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#include "sve_struct_vect_7.c" + +#define N 93 + +TYPE a[N], b[N], c[N], d[N], e[N * 4]; + +void __attribute__ ((noinline, noclone)) +init_array (TYPE *array, int n, TYPE base, TYPE step) +{ + for (int i = 0; i < n; ++i) + array[i] = base + step * i; +} + +void __attribute__ ((noinline, noclone)) +check_array (TYPE *array, int n, TYPE base, TYPE step) +{ + for (int i = 0; i < n; ++i) + if (array[i] != (TYPE) (base + step * i)) + __builtin_abort (); +} + +int __attribute__ ((optimize (1))) +main (void) +{ + init_array (e, 2 * N, 11, 5); + f2 (a, b, e, N); + check_array (a, N, 11, 10); + check_array (b, N, 16, 10); + + init_array (e, 3 * N, 7, 6); + f3 (a, b, c, e, N); + check_array (a, N, 7, 18); + check_array (b, N, 13, 18); + check_array (c, N, 19, 18); + + init_array (e, 4 * N, 4, 11); + f4 (a, b, c, d, e, N); + check_array (a, N, 4, 44); + check_array (b, N, 15, 44); + check_array (c, N, 26, 44); + check_array (d, N, 37, 44); + + init_array (a, N, 2, 8); + init_array (b, N, 6, 8); + g2 (a, b, e, N); + check_array (e, 2 * N, 2, 4); + + init_array (a, N, 4, 15); + init_array (b, N, 9, 15); + init_array (c, N, 14, 15); + g3 (a, b, c, e, N); + check_array (e, 3 * N, 4, 5); + + init_array (a, N, 14, 36); + init_array (b, N, 23, 36); + init_array (c, N, 32, 36); + init_array (d, N, 41, 36); + g4 (a, b, c, d, e, N); + check_array (e, 4 * N, 14, 9); + + return 0; +} Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_8.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_8.c 2017-11-08 15:06:27.251849138 +0000 @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned short +#define ITYPE short +#include "sve_struct_vect_7.c" + +/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_8_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_8_run.c 2017-11-08 15:06:27.251849138 +0000 @@ -0,0 +1,6 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned short +#define ITYPE short +#include "sve_struct_vect_7_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_9.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_9.c 2017-11-08 15:06:27.251849138 +0000 @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned int +#define ITYPE int +#include "sve_struct_vect_7.c" + +/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_9_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_9_run.c 2017-11-08 15:06:27.251849138 +0000 @@ -0,0 +1,6 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned int +#define ITYPE int +#include "sve_struct_vect_7_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_10.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_10.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned long +#define ITYPE long +#include "sve_struct_vect_7.c" + +/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_10_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_10_run.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,6 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE unsigned long +#define ITYPE long +#include "sve_struct_vect_7_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_11.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_11.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE _Float16 +#define ITYPE short +#include "sve_struct_vect_7.c" + +/* { dg-final { scan-assembler {\tld2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_11_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_11_run.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,6 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE _Float16 +#define ITYPE short +#include "sve_struct_vect_7_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_12.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_12.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE float +#define ITYPE int +#include "sve_struct_vect_7.c" + +/* { dg-final { scan-assembler {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_12_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_12_run.c 2017-11-08 15:06:27.248849138 +0000 @@ -0,0 +1,6 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE float +#define ITYPE int +#include "sve_struct_vect_7_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_13.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_13.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE double +#define ITYPE long +#include "sve_struct_vect_7.c" + +/* { dg-final { scan-assembler {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ +/* { dg-final { scan-assembler {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_13_run.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_13_run.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,6 @@ +/* { dg-do run { target aarch64_sve_hw } } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve --save-temps" } */ + +#define TYPE double +#define ITYPE long +#include "sve_struct_vect_7_run.c" Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_14.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_14.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,72 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve -msve-vector-bits=256 --save-temps" } */ + +#define TYPE unsigned char +#define NAME(X) qi_##X +#include "sve_struct_vect_1.c" +#undef NAME +#undef TYPE + +#define TYPE unsigned short +#define NAME(X) hi_##X +#include "sve_struct_vect_1.c" +#undef NAME +#undef TYPE + +#define TYPE unsigned int +#define NAME(X) si_##X +#include "sve_struct_vect_1.c" +#undef NAME +#undef TYPE + +#define TYPE unsigned long +#define NAME(X) di_##X +#include "sve_struct_vect_1.c" +#undef NAME +#undef TYPE + +#define TYPE _Float16 +#define NAME(X) hf_##X +#include "sve_struct_vect_1.c" +#undef NAME +#undef TYPE + +#define TYPE float +#define NAME(X) sf_##X +#include "sve_struct_vect_1.c" +#undef NAME +#undef TYPE + +#define TYPE double +#define NAME(X) df_##X +#include "sve_struct_vect_1.c" +#undef NAME +#undef TYPE + +/* { dg-final { scan-assembler-times {\tld2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tld2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_15.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_15.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,32 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve -msve-vector-bits=512 --save-temps" } */ + +#include "sve_struct_vect_14.c" + +/* { dg-final { scan-assembler-times {\tld2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tld2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_16.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_16.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,32 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve -msve-vector-bits=1024 --save-temps" } */ + +#include "sve_struct_vect_14.c" + +/* { dg-final { scan-assembler-times {\tld2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tld2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ Index: gcc/testsuite/gcc.target/aarch64/sve_struct_vect_17.c =================================================================== --- /dev/null 2017-11-08 11:04:45.353113300 +0000 +++ gcc/testsuite/gcc.target/aarch64/sve_struct_vect_17.c 2017-11-08 15:06:27.249849138 +0000 @@ -0,0 +1,32 @@ +/* { dg-do assemble } */ +/* { dg-options "-O2 -ftree-vectorize -march=armv8-a+sve -msve-vector-bits=2048 --save-temps" } */ + +#include "sve_struct_vect_14.c" + +/* { dg-final { scan-assembler-times {\tld2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tld4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7]/z, \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst2b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst3b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tst4b\t{z[0-9]+.b - z[0-9]+.b}, p[0-7], \[x[0-9]+\]\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tld2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4h\t{z[0-9]+.h - z[0-9]+.h}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4w\t{z[0-9]+.s - z[0-9]+.s}, p[0-7], \[x[0-9]+\]\n} 2 } } */ + +/* { dg-final { scan-assembler-times {\tld2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tld4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7]/z, \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst2d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst3d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {\tst4d\t{z[0-9]+.d - z[0-9]+.d}, p[0-7], \[x[0-9]+\]\n} 2 } } */