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Wed, 29 Nov 2017 11:26:50 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20171129112649eucas1p16bc5ac7a6237eba11fc42ec2bd38dc52~7iuOFD5hR0227002270eucas1p1V; Wed, 29 Nov 2017 11:26:49 +0000 (GMT) X-AuditID: cbfec7f2-f793b6d000003243-43-5a1e997a6dcb Received: from eusync4.samsung.com ( [203.254.199.214]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 0A.C3.18832.9799E1A5; Wed, 29 Nov 2017 11:26:49 +0000 (GMT) Received: from AMDC2765.digital.local ([106.116.147.25]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0P06008RTFSLHZ20@eusync4.samsung.com>; Wed, 29 Nov 2017 11:26:49 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Krzysztof Kozlowski , Bartlomiej Zolnierkiewicz , Chanwoo Choi , Inki Dae Subject: [PATCH v2 2/6] arm64: dts: exynos: Add DISP power domain to Exynos 5433 SoC Date: Wed, 29 Nov 2017 12:26:34 +0100 Message-id: <20171129112638.15813-3-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.15.0 In-reply-to: <20171129112638.15813-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrCIsWRmVeSWpSXmKPExsWy7djP87pVM+WiDB4sEbDYOGM9q8X1L89Z LSbdn8Bicf78BnaLGef3MVmsPXKX3eLwm3ZWB3aPTas62Tz6tqxi9Pi8SS6AOYrLJiU1J7Ms tUjfLoEr4+Sb56wFuyQrNr74zdrA+Fe4i5GTQ0LAROLo04uMELaYxIV769lAbCGBpYwS0/ZU dDFyAdmfGSVOn1zFDNPw9u4sVojEMkaJJyfuM0M4DUwSV7Z3sYNUsQkYSnS97QIbJSKgKvG5 bQE7SBGzQBuTxK5bbawgCWGBMImXi1uZQGwWoKLry66BreAVsJX4N/8FK8Q6eYnF33eCDeIU sJO4dbABbLWEwF9WifVT2qBucpF4cbaTDcIWlnh1fAs7hC0j0dlxkAnC7meUaGrVhrBnMEqc e8sLYVtLHD5+EWwZswCfxKRt04FmcgDFeSU62oQgSjwk2v++hRrpKPGtrRnq44mMEncetDFO YJRewMiwilEktbQ4Nz212FivODG3uDQvXS85P3cTIzAuT/87/mkH49cTVocYBTgYlXh4L6yQ jRJiTSwrrsw9xCjBwawkwrvBSy5KiDclsbIqtSg/vqg0J7X4EKM0B4uSOK9tVFukkEB6Yklq dmpqQWoRTJaJg1OqgTEiMJxFc0NaSmmRcpYZB+PJ5PILPIdllZoW+2YXqst/WfZNP7fv6WuF ua88j9QwTgha2nXpbcfEnusxP321V9TtS7Up1fhYvlBq9xqHKcIBO+0+8uxJ5xXWW9ddyOVz VOFU+jVhF5bN83YVnHEQNvdhSPeZ/nTuMamGGfWSeiuXV+fFupiKKrEUZyQaajEXFScCAOTx xBvHAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupkluLIzCtJLcpLzFFi42I5/e/4Nd3KmXJRBq9faVpsnLGe1eL6l+es FpPuT2CxOH9+A7vFjPP7mCzWHrnLbnH4TTurA7vHplWdbB59W1YxenzeJBfAHMVlk5Kak1mW WqRvl8CVcfLNc9aCXZIVG1/8Zm1g/CvcxcjJISFgIvH27ixWCFtM4sK99WwgtpDAEkaJzkOC XYxcQHYTk8SNgxeYQRJsAoYSXW+7wIpEBFQlPrctYAcpYhboYJL4d6cFLCEsECbxcnErE4jN AlR0fdk1sGZeAVuJf/NfQG2Tl1j8fSdYPaeAncStgw2sEJttJa49Osk8gZF3ASPDKkaR1NLi 3PTcYkO94sTc4tK8dL3k/NxNjMAA2nbs5+YdjJc2Bh9iFOBgVOLh1VgtGyXEmlhWXJl7iFGC g1lJhHeDl1yUEG9KYmVValF+fFFpTmrxIUZpDhYlcd7ePasjhQTSE0tSs1NTC1KLYLJMHJxS DYz8yhySoZEvLrHuapFNCXjqLL/pSGvApod/O5yMN9pP4lp0rW/D9tMqW8+8j5x15bjoIV+v XSqGHvx5X3aUNGw4UZ81VWnV4buPb5QvZ+TLOGkX+mTPmx/xLduiRNkWKzpcCXs43fnlovuM nMYcAus3NdUfmjvzn/SprzNWzN6x+8HtuM2T44J/KLEUZyQaajEXFScCAGf+dHAcAgAA X-CMS-MailID: 20171129112649eucas1p16bc5ac7a6237eba11fc42ec2bd38dc52 X-Msg-Generator: CA CMS-TYPE: 201P X-CMS-RootMailID: 20171129112649eucas1p16bc5ac7a6237eba11fc42ec2bd38dc52 X-RootMTR: 20171129112649eucas1p16bc5ac7a6237eba11fc42ec2bd38dc52 References: <20171129112638.15813-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org This patch adds support for DISP power domain to Exynos 5433 SoCs, which contains following devices: a clock controller, two display controllers (DECON and DECON TV), their SYSMMUs, MIC, DSI and HDMI video devices. OCSigned-off-by: Marek Szyprowski --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Chanwoo Choi diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 2a03be0c9ae7..95f30ccc00a3 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -386,6 +386,7 @@ <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>, <&cmu_mif CLK_ACLK_DISP_333>; + power-domains = <&pd_disp>; }; cmu_aud: clock-controller@114c0000 { @@ -551,6 +552,13 @@ label = "GSCL"; }; + pd_disp: power-domain@105c4080 { + compatible = "samsung,exynos5433-pd"; + reg = <0x105c4080 0x20>; + #power-domain-cells = <0>; + label = "DISP"; + }; + tmu_atlas0: tmu@10060000 { compatible = "samsung,exynos5433-tmu"; reg = <0x10060000 0x200>; @@ -754,6 +762,7 @@ clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x", "pclk_smmu_decon0x", "sclk_decon_vclk", "sclk_decon_eclk"; + power-domains = <&pd_disp>; interrupt-names = "fifo", "vsync", "lcd_sys"; interrupts = , , @@ -791,6 +800,7 @@ "aclk_xiu_decon0x", "pclk_smmu_decon0x", "sclk_decon_vclk", "sclk_decon_eclk"; samsung,disp-sysreg = <&syscon_disp>; + power-domains = <&pd_disp>; interrupt-names = "fifo", "vsync", "lcd_sys"; interrupts = , , @@ -816,6 +826,7 @@ "phyclk_mipidphy0_rxclkesc0", "sclk_rgb_vclk_to_dsim0", "sclk_mipi"; + power-domains = <&pd_disp>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -839,6 +850,7 @@ clocks = <&cmu_disp CLK_PCLK_MIC0>, <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>; clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0"; + power-domains = <&pd_disp>; samsung,disp-syscon = <&syscon_disp>; status = "disabled"; @@ -980,6 +992,7 @@ clock-names = "pclk", "aclk"; clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>; + power-domains = <&pd_disp>; #iommu-cells = <0>; }; @@ -991,6 +1004,7 @@ clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>, <&cmu_disp CLK_ACLK_SMMU_DECON1X>; #iommu-cells = <0>; + power-domains = <&pd_disp>; }; sysmmu_tv0x: sysmmu@13a20000 { @@ -1001,6 +1015,7 @@ clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>, <&cmu_disp CLK_ACLK_SMMU_TV0X>; #iommu-cells = <0>; + power-domains = <&pd_disp>; }; sysmmu_tv1x: sysmmu@13a30000 { @@ -1011,6 +1026,7 @@ clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>, <&cmu_disp CLK_ACLK_SMMU_TV1X>; #iommu-cells = <0>; + power-domains = <&pd_disp>; }; sysmmu_gscl0: sysmmu@13c80000 {