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[209.132.180.67]) by mx.google.com with ESMTP id w13si5070070pgm.393.2017.12.01.09.03.27; Fri, 01 Dec 2017 09:03:28 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=e4k9J/iC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751801AbdLARD0 (ORCPT + 28 others); Fri, 1 Dec 2017 12:03:26 -0500 Received: from mail-wr0-f195.google.com ([209.85.128.195]:34207 "EHLO mail-wr0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751855AbdLARCf (ORCPT ); Fri, 1 Dec 2017 12:02:35 -0500 Received: by mail-wr0-f195.google.com with SMTP id y21so10785752wrc.1 for ; Fri, 01 Dec 2017 09:02:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rPpiBZ0p5nkk9kadXe66AnmTeg2Alwe1QQ7ulrca7vA=; b=e4k9J/iCLO90Za0yBVP+sfCdrPqQ1gj0hicQ+i0qzBXHiTFSn7OrY5qAA8Q95bWIxw r4YkD5fnNDq0TxpL5gJRPnPCUMZE2ZcJHAT7eyKjZ3GZfeVh6caJpRm6bCUSVFIVHsMm QLyb+sxbFwSVv4lo9gpohy2XluWKmFcbnbl4s= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rPpiBZ0p5nkk9kadXe66AnmTeg2Alwe1QQ7ulrca7vA=; b=bQm8MWkm+/cZfR7KojoJZiAXYROMImKGDxCFPXXXWnqTsKyLW6nJtyB7oCKsXZqZIT D0vi9INE9DVJlw6EnMDBBc3iuVYvgRoqrY2GwF41SqRGzyj+tZKwy3guroDHymTkCg41 JfvjDW5nIv6tYH7Uv3wbvx0QzW/bxBAfkZ16ngqiY1B8ZC0VNQ/rWPKZ4Xbo6MzC+0zA u4zMICOSOmZlp9xZ0nESZna01H06IauHMZFcYb0kvJy5lcKnEyZoT/ZYUHhfWM04nA5C y85bDZIVU8YpcAJTo6MMKLPld1LGBkswd0Isa0dYyQ0tW88D2J9DarzjMn7NAidUnG60 czUw== X-Gm-Message-State: AJaThX69pRynjshdGGfZfmbcCEVUQb8/cwLIceyDssaJ7S2ZLq0/sFvl VBB7H6wK/t9LM/4CeKSvUkUWHg== X-Received: by 10.223.181.150 with SMTP id c22mr6635143wre.0.1512147753833; Fri, 01 Dec 2017 09:02:33 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id 2sm1535253wmk.28.2017.12.01.09.02.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 01 Dec 2017 09:02:33 -0800 (PST) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org, robh@kernel.org Cc: mturquette@baylibre.com, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v10 5/6] dt-bindings: mailbox: qcom: Document the APCS clock binding Date: Fri, 1 Dec 2017 19:02:23 +0200 Message-Id: <20171201170224.25053-6-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171201170224.25053-1-georgi.djakov@linaro.org> References: <20171201170224.25053-1-georgi.djakov@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the binding documentation for APCS to mention that the APCS hardware block also expose a clock controller functionality. The APCS clock controller is a mux and half-integer divider. It has the main CPU PLL as an input and provides the clock for the application CPU. Signed-off-by: Georgi Djakov --- .../bindings/mailbox/qcom,apcs-kpss-global.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt index fb961c310f44..16964f0c1773 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt @@ -15,12 +15,21 @@ platforms. Usage: required Value type: Definition: must specify the base address and size of the global block +- clocks: + Usage: required if #clocks-cells property is present + Value type: + Definition: phandle to the input PLL, which feeds the APCS mux/divider - #mbox-cells: Usage: required Value type: Definition: as described in mailbox.txt, must be 1 +- #clock-cells: + Usage: optional + Value type: + Definition: as described in clock.txt, must be 0 + = EXAMPLE The following example describes the APCS HMSS found in MSM8996 and part of the @@ -44,3 +53,12 @@ GLINK RPM referencing the "rpm_hlos" doorbell therein. mbox-names = "rpm_hlos"; }; +Below is another example of the APCS binding on MSM8916 platforms: + + apcs: mailbox@b011000 { + compatible = "qcom,msm8916-apcs-kpss-global"; + reg = <0xb011000 0x1000>; + #mbox-cells = <1>; + clocks = <&a53pll>; + #clock-cells = <0>; + };