From patchwork Sat Dec 2 11:23:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 120418 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp2253008qgn; Sat, 2 Dec 2017 03:25:19 -0800 (PST) X-Google-Smtp-Source: AGs4zMbZW7QGQIZ2n6zGP1Oe8TodM3nXosRnFb8YbQmpai8+tEjsu6rp/FM1McvYvW7P46JjpGsU X-Received: by 10.99.55.92 with SMTP id g28mr8826067pgn.293.1512213919680; Sat, 02 Dec 2017 03:25:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512213919; cv=none; d=google.com; s=arc-20160816; b=TZtzdYlDHkYm9V8cMzEGZHmySiJkQtKKGr/THD5JGxtf6LHl0cwSKAdp2wSAGaXPIn /fvAke6K7OV1b6edS4to/+Q7hzfiODnzQnvY8sDAdTRkNUPKdKkQwpY9AJ2OsAc70lhQ +y4u6CDgHCQdC5l/cD7oxpNL+iWR0SUFOhi+qtZD4elzNoD8lYbSQ3+ES3BmyuTo5qHF 4Q3w3ijMaKXJdySK3lic95/ZhmO7NMXPifmtZF0Cuec5BxnhvQSkwyqmnVPGOAlJsEbH 1BwkMx6UK90MqCfoRu4PDc54XKodBS+V42L7yTm307hPDjxHD2qURWg3M3IZlzhlse0q H7jw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=iBnWbuqPtoXHl2tPF+FS5dKXVLxQtaqAQZqv8fiUA/k=; b=fyIr/HzQDJpDvibfe25j9CL2rE+hTP+E9fcluKp0r528d73/GRVrvYasJ1PM5gOU1B 8z78i5TmYxEHTi8ozAMvGGv1d+ZOl8A50WcDXnBfqTU2UXANN4z/VtEBFW+TLJ9qEzqf URwdQU1rrrQm07/gK4bhEygdVYzLpOH5o141d2wDd8eHz6u9jssGgt2XN1MqO1ztZhCF FIxpdUPdpOH4ehv+PA0rDMXn1VEmB64JiBShjdSrS24PtBdMLTAjq2WG4d1xpJqJtPAN KKmUx6Unft5dBlbM8GTOaHjMR2wM81vxsOBo73KHyCFyAJFKpgfyCSTTSyVnAgkeWb9k xQCw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HMM6yddC; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 4si6308695plc.324.2017.12.02.03.25.19; Sat, 02 Dec 2017 03:25:19 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=HMM6yddC; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751647AbdLBLZS (ORCPT + 6 others); Sat, 2 Dec 2017 06:25:18 -0500 Received: from mail-lf0-f66.google.com ([209.85.215.66]:41451 "EHLO mail-lf0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751649AbdLBLZR (ORCPT ); Sat, 2 Dec 2017 06:25:17 -0500 Received: by mail-lf0-f66.google.com with SMTP id f18so14347019lfg.8 for ; Sat, 02 Dec 2017 03:25:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=Xx82ck4tFUNjV4/remta67DtwI+VWE28tgad8ANbD8g=; b=HMM6yddC0O8jUsXZcj3k8WysNh90MAXVHaFauVgleHTcRZYGNoTXOekJjIpqLV8Rra tEwHlLLZSqmoj80R5iDcoOqGaDr0idpBqsIIrHBBpO9ih7rkjrrqHhB1ntt0GZtMgYS7 A+o4sW4YtsMG7Ao/t+3ox/ksoZOVVnS9LOUA8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Xx82ck4tFUNjV4/remta67DtwI+VWE28tgad8ANbD8g=; b=m0B8LWFDga1Hi0u67a5Fq7lFBuQ6/ft9hEIWIm/EGFLfUHxKedYI1D/ATU6b00BpgZ tQKaPhlSf8ClDWJW9a+5JEjOrJnCxY9yhoZ/Vtnxfizp9NxLFosUlb3aw5nY/r301uFJ i9cp2rhmh/onBoiD4ppe9YqlMdBcWeJkDaXyjhMVFXoIUKr9/CqSasR5dea56TctAJnc 8rfjhpnSk79O81sLOrpk1AwsDWwFtFZFB0ZF0/BGnuWcn5NRu6ExjQ2oP7YgevPOz/U1 urVOBkzYyjR/Ukcyv3mrjG5PenrH8L851PaNwSYWB4WrI9VcuDND8K1gQw6tKi7Ytkiy alDg== X-Gm-Message-State: AJaThX4UcxXf321aP/pi4VCeQ46LGbfwMHlm8uPKIQ57SqlDGtLYwNjZ LuaRiRLsM+F5CoaMVX9bHn6I9g== X-Received: by 10.25.20.81 with SMTP id k78mr5474156lfi.146.1512213915440; Sat, 02 Dec 2017 03:25:15 -0800 (PST) Received: from localhost.localdomain (c-567171d5.014-348-6c756e10.cust.bredbandsbolaget.se. [213.113.113.86]) by smtp.gmail.com with ESMTPSA id 2sm1733474lju.17.2017.12.02.03.25.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 02 Dec 2017 03:25:14 -0800 (PST) From: Linus Walleij To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: linux-gpio@vger.kernel.org, Linus Walleij , devicetree@vger.kernel.org Subject: [PATCH] pinctrl: gemini: Support drive strength setting Date: Sat, 2 Dec 2017 12:23:09 +0100 Message-Id: <20171202112309.5726-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.14.3 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Gemini pin controller can set drive strength for a few select groups of pins (not individually). Implement this for GMAC0 and 1 (ethernet ports), IDE and PCI. Cc: devicetree@vger.kernel.org Signed-off-by: Linus Walleij --- The DT binding part is just using generic bindings, so should be pretty uncontroversial. --- .../bindings/pinctrl/cortina,gemini-pinctrl.txt | 3 + drivers/pinctrl/pinctrl-gemini.c | 81 ++++++++++++++++++++++ 2 files changed, 84 insertions(+) -- 2.14.3 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt index d857b67fab72..4346ff2dd8e6 100644 --- a/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/cortina,gemini-pinctrl.txt @@ -17,6 +17,9 @@ and generic pin config nodes. Supported configurations: - skew-delay is supported on the Ethernet pins +- drive-strength with 4, 8, 12 or 16 mA as argument is supported for + entire groups on the groups "idegrp", "gmii_gmac0_grp", "gmii_gmac1_grp" + and "pcigrp". Example: diff --git a/drivers/pinctrl/pinctrl-gemini.c b/drivers/pinctrl/pinctrl-gemini.c index c11b8f14d841..56db4e77b220 100644 --- a/drivers/pinctrl/pinctrl-gemini.c +++ b/drivers/pinctrl/pinctrl-gemini.c @@ -67,6 +67,9 @@ struct gemini_pmx { * elements in .pins so we can iterate over that array * @mask: bits to clear to enable this when doing pin muxing * @value: bits to set to enable this when doing pin muxing + * @driving_mask: bitmask for the IO Pad driving register for this + * group, if it supports altering the driving strength of + * its lines. */ struct gemini_pin_group { const char *name; @@ -74,12 +77,14 @@ struct gemini_pin_group { const unsigned int num_pins; u32 mask; u32 value; + u32 driving_mask; }; /* Some straight-forward control registers */ #define GLOBAL_WORD_ID 0x00 #define GLOBAL_STATUS 0x04 #define GLOBAL_STATUS_FLPIN BIT(20) +#define GLOBAL_IODRIVE 0x10 #define GLOBAL_GMAC_CTRL_SKEW 0x1c #define GLOBAL_GMAC0_DATA_SKEW 0x20 #define GLOBAL_GMAC1_DATA_SKEW 0x24 @@ -738,6 +743,7 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = { /* Conflict with all flash usage */ .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, + .driving_mask = GENMASK(21, 20), }, { .name = "satagrp", @@ -753,6 +759,7 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = { .name = "gmii_gmac0_grp", .pins = gmii_gmac0_3512_pins, .num_pins = ARRAY_SIZE(gmii_gmac0_3512_pins), + .driving_mask = GENMASK(17, 16), }, { .name = "gmii_gmac1_grp", @@ -760,6 +767,7 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = { .num_pins = ARRAY_SIZE(gmii_gmac1_3512_pins), /* Bring out RGMII on the GMAC1 pins */ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, + .driving_mask = GENMASK(19, 18), }, { .name = "pcigrp", @@ -767,6 +775,7 @@ static const struct gemini_pin_group gemini_3512_pin_groups[] = { .num_pins = ARRAY_SIZE(pci_3512_pins), /* Conflict only with GPIO2 */ .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, + .driving_mask = GENMASK(23, 22), }, { .name = "lpcgrp", @@ -1671,6 +1680,7 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = { /* Conflict with all flash usage */ .value = IDE_PADS_ENABLE | NAND_PADS_DISABLE | PFLASH_PADS_DISABLE | SFLASH_PADS_DISABLE, + .driving_mask = GENMASK(21, 20), }, { .name = "satagrp", @@ -1686,6 +1696,7 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = { .name = "gmii_gmac0_grp", .pins = gmii_gmac0_3516_pins, .num_pins = ARRAY_SIZE(gmii_gmac0_3516_pins), + .driving_mask = GENMASK(17, 16), }, { .name = "gmii_gmac1_grp", @@ -1693,6 +1704,7 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = { .num_pins = ARRAY_SIZE(gmii_gmac1_3516_pins), /* Bring out RGMII on the GMAC1 pins */ .value = GEMINI_GMAC_IOSEL_GMAC0_GMAC1_RGMII, + .driving_mask = GENMASK(19, 18), }, { .name = "pcigrp", @@ -1700,6 +1712,7 @@ static const struct gemini_pin_group gemini_3516_pin_groups[] = { .num_pins = ARRAY_SIZE(pci_3516_pins), /* Conflict only with GPIO2 */ .value = PCI_PADS_ENABLE | PCI_CLK_PAD_ENABLE, + .driving_mask = GENMASK(23, 22), }, { .name = "lpcgrp", @@ -2393,9 +2406,77 @@ static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, return ret; } +static int gemini_pinconf_group_set(struct pinctrl_dev *pctldev, + unsigned selector, + unsigned long *configs, + unsigned num_configs) +{ + struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); + const struct gemini_pin_group *grp = NULL; + enum pin_config_param param; + u32 arg; + u32 val; + int i; + + if (pmx->is_3512) + grp = &gemini_3512_pin_groups[selector]; + if (pmx->is_3516) + grp = &gemini_3516_pin_groups[selector]; + + /* First figure out if this group supports configs */ + if (!grp->driving_mask) { + dev_err(pmx->dev, "pin config group \"%s\" does " + "not support drive strength setting\n", + grp->name); + return -EINVAL; + } + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_DRIVE_STRENGTH: + switch (arg) { + case 4: + val = 0; + break; + case 8: + val = 1; + break; + case 12: + val = 2; + break; + case 16: + val = 3; + break; + default: + dev_err(pmx->dev, + "invalid drive strength %d mA\n", + arg); + return -ENOTSUPP; + } + val <<= (ffs(grp->driving_mask) - 1); + regmap_update_bits(pmx->map, GLOBAL_IODRIVE, + grp->driving_mask, + val); + dev_info(pmx->dev, + "set group %s to %d mA drive strength mask %08x val %08x\n", + grp->name, arg, grp->driving_mask, val); + break; + default: + dev_err(pmx->dev, "invalid config param %04x\n", param); + return -ENOTSUPP; + } + } + + return 0; +} + static const struct pinconf_ops gemini_pinconf_ops = { .pin_config_get = gemini_pinconf_get, .pin_config_set = gemini_pinconf_set, + .pin_config_group_set = gemini_pinconf_group_set, .is_generic = true, };