From patchwork Tue Dec 5 15:47:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgi Djakov X-Patchwork-Id: 120698 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp5906508qgn; Tue, 5 Dec 2017 07:47:46 -0800 (PST) X-Google-Smtp-Source: AGs4zMZuhia6A+JPOWJyFtpoiFY6oJW2h6zpqthRRNIY+hwqud3d7QIH4xeNkDE7yXExgHVvyisK X-Received: by 10.84.196.131 with SMTP id l3mr18556664pld.194.1512488866054; Tue, 05 Dec 2017 07:47:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512488866; cv=none; d=google.com; s=arc-20160816; b=0C6abka4hWeRg1bmR3hpwfAwMboKEhCRc/GQxZR5YZwoePhFO5xrbbgld9gj3cAH4p Ot7iiAYM+sjewbmh9tlKDTd3clnM2ZfkZuRAoZtsKetFRN8MF23V7rvGMEatPaaZO5V6 mkabWYAaqSl87wVktbSMC4LXcy3BXnTcmJCS5Qlk1uqm2+CH4IwSR2iRFVkDz72/Ht9H OHaszfAb+578OM12hBQCKcj/gdVbXrApMkL5Igry9ikF+pwG+W8myOD8+OeIyMoVLhiF Du+QiaIAZhLL/gn5eW6ohwKBy6FjDCHaRx4oXcIJfEuGwRFTtjr5kjql2nJ2bDRq1WI7 eaIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature:arc-authentication-results; bh=sLiHYlrdmOvPNh5ad8pAQT+f1eJO0MEZXul9iptpvtU=; b=DnWzEGJgvAJO7gmaMuXvnHgE2UnnIAxBxCd57d2KzT50zV6+L0x2oWwUZUuu1YgA7u L93FR/B3yXYlCkJh/Ac9wLMImo8bvsNrnxy+xFxzPvpPsnmyFpy+a1+mXw9YWUUjZnIN 9Xvet6NUoSgqH8ZkF7h+C22tpa1IcG7Ydj4qbq5nIRK7LiiTO87TYxTu66mAlnG5FTVJ 7t484fQR7vOwIQmdEQHGA79RcyugT3yvXsrFWw1bmvwnKpo8/0qXOeWQZLIwuoKFTmiD Kd3baHDbqqdrIb7LgbV4MuHUUyNN5LmdRJM+C4RdO1yppWPXdoNu66BGBq3fjq3TjY0G cVdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Ej075zrk; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o2si235836pll.585.2017.12.05.07.47.45; Tue, 05 Dec 2017 07:47:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Ej075zrk; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753018AbdLEPro (ORCPT + 10 others); Tue, 5 Dec 2017 10:47:44 -0500 Received: from mail-wr0-f194.google.com ([209.85.128.194]:35463 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753138AbdLEPrO (ORCPT ); Tue, 5 Dec 2017 10:47:14 -0500 Received: by mail-wr0-f194.google.com with SMTP id g53so797264wra.2 for ; Tue, 05 Dec 2017 07:47:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=O3kvCUmFAZqwfM34RCzUQYzGXki30RpsNGgQD7V8sNA=; b=Ej075zrksIFAF0xXXm49XpQhFIf88ij99QGJUM1Ggg+BpmM4+9hkdtFKGt/vBshTuD cdmv0dPRLGL43zmMsn4hncmEO7bqOvuK51HfCQUOnPBfVhIlLdbuKef9zYTfdNvRGQbi QeFsjrzNLBA1CTL/JeEuGgbRzlH4N6HrAIWf0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=O3kvCUmFAZqwfM34RCzUQYzGXki30RpsNGgQD7V8sNA=; b=sQpNtdMJVprfNRHkW2bqtJq7DJu//WjaXmn9xN7ptAiKlqEvZExJMB5DiW8u7WTUBG IonP5K2acyvKVimdkW4OnXsFW9SpljpA9fjl95tHJARRJDreAkZt26eClweVqF2E9UQt wxp2JWPRgdSD5V9jIJ/PHB8L8JNCTnUha1sI01jT9mCClwLdj3zOfeG2lXlYQKXjsBKL 8baPCBM9YGhLTRe87E3dptY1az2UEfYF4UFzMp1R48+w3QdRDA+TZVGephy7/8eOW4Fi caUBgCWb5uu9L/AIQ1MYfpZyIKsj+B/G9A0jIcNjejHrgqj35bdJZsEv+rrfi82V/1WY 7l+A== X-Gm-Message-State: AJaThX6ndjxD8C1ZMb0/SRPFuPUz8DuItzH30a6dIJKgNdpTxl4xMyFQ Dj7rwAt5VOC3u4qoHOepmyxNeQ== X-Received: by 10.223.185.3 with SMTP id k3mr17372892wrf.40.1512488832778; Tue, 05 Dec 2017 07:47:12 -0800 (PST) Received: from localhost.localdomain ([212.45.67.2]) by smtp.googlemail.com with ESMTPSA id v47sm500946wrc.13.2017.12.05.07.47.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 05 Dec 2017 07:47:11 -0800 (PST) From: Georgi Djakov To: sboyd@codeaurora.org, jassisinghbrar@gmail.com, bjorn.andersson@linaro.org Cc: mturquette@baylibre.com, robh@kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, georgi.djakov@linaro.org Subject: [PATCH v11 6/6] clk: qcom: Add APCS clock controller support Date: Tue, 5 Dec 2017 17:47:01 +0200 Message-Id: <20171205154701.27730-7-georgi.djakov@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171205154701.27730-1-georgi.djakov@linaro.org> References: <20171205154701.27730-1-georgi.djakov@linaro.org> Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a driver for the APCS clock controller. It is part of the APCS hardware block, which among other things implements also a combined mux and half integer divider functionality. It can choose between a fixed-rate clock or the dedicated APCS (A53) PLL. The source and the divider can be set both at the same time. This is required for enabling CPU frequency scaling on MSM8916-based platforms. Signed-off-by: Georgi Djakov --- drivers/clk/qcom/Kconfig | 11 +++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/apcs-msm8916.c | 149 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 161 insertions(+) create mode 100644 drivers/clk/qcom/apcs-msm8916.c -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 81ac7b9378fe..255023b439c9 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -22,6 +22,17 @@ config QCOM_A53PLL Say Y if you want to support higher CPU frequencies on MSM8916 devices. +config QCOM_CLK_APCS_MSM8916 + bool "MSM8916 APCS Clock Controller" + depends on COMMON_CLK_QCOM + depends on QCOM_APCS_IPC + default ARCH_QCOM + help + Support for the APCS Clock Controller on msm8916 devices. The + APCS is managing the mux and divider which feeds the CPUs. + Say Y if you want to support CPU frequency scaling on devices + such as msm8916. + config QCOM_CLK_RPM tristate "RPM based Clock Controller" depends on COMMON_CLK_QCOM && MFD_QCOM_RPM diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 7c51d877f967..0408cebf38d4 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -34,5 +34,6 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o +obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o diff --git a/drivers/clk/qcom/apcs-msm8916.c b/drivers/clk/qcom/apcs-msm8916.c new file mode 100644 index 000000000000..832172c2fc8b --- /dev/null +++ b/drivers/clk/qcom/apcs-msm8916.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm APCS clock controller driver + * + * Copyright (c) 2017, Linaro Limited + * Author: Georgi Djakov + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "clk-regmap.h" +#include "clk-regmap-mux-div.h" + +enum { + P_GPLL0, + P_A53PLL, +}; + +static const struct parent_map gpll0_a53cc_map[] = { + { P_GPLL0, 4 }, + { P_A53PLL, 5 }, +}; + +static const char * const gpll0_a53cc[] = { + "gpll0_vote", + "a53pll", +}; + +/* + * We use the notifier function for switching to a temporary safe configuration + * (mux and divider), while the A53 PLL is reconfigured. + */ +static int a53cc_notifier_cb(struct notifier_block *nb, unsigned long event, + void *data) +{ + int ret = 0; + struct clk_regmap_mux_div *md = container_of(nb, + struct clk_regmap_mux_div, + clk_nb); + if (event == PRE_RATE_CHANGE) + /* set the mux and divider to safe frequency (400mhz) */ + ret = __mux_div_set_src_div(md, 4, 3); + + return notifier_from_errno(ret); +} + +static int qcom_apcs_msm8916_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device *parent = dev->parent; + struct clk_regmap_mux_div *a53cc; + struct regmap *regmap; + struct clk_init_data init = { }; + int ret; + + regmap = dev_get_regmap(parent, NULL); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err(dev, "failed to get regmap: %d\n", ret); + return ret; + } + + a53cc = devm_kzalloc(dev, sizeof(*a53cc), GFP_KERNEL); + if (!a53cc) + return -ENOMEM; + + init.name = "a53mux"; + init.parent_names = gpll0_a53cc; + init.num_parents = ARRAY_SIZE(gpll0_a53cc); + init.ops = &clk_regmap_mux_div_ops; + init.flags = CLK_SET_RATE_PARENT; + + a53cc->clkr.hw.init = &init; + a53cc->clkr.regmap = regmap; + a53cc->reg_offset = 0x50; + a53cc->hid_width = 5; + a53cc->hid_shift = 0; + a53cc->src_width = 3; + a53cc->src_shift = 8; + a53cc->parent_map = gpll0_a53cc_map; + + a53cc->pclk = devm_clk_get(parent, NULL); + if (IS_ERR(a53cc->pclk)) { + ret = PTR_ERR(a53cc->pclk); + dev_err(dev, "failed to get clk: %d\n", ret); + return ret; + } + + a53cc->clk_nb.notifier_call = a53cc_notifier_cb; + ret = clk_notifier_register(a53cc->pclk, &a53cc->clk_nb); + if (ret) { + dev_err(dev, "failed to register clock notifier: %d\n", ret); + return ret; + } + + ret = devm_clk_register_regmap(dev, &a53cc->clkr); + if (ret) { + dev_err(dev, "failed to register regmap clock: %d\n", ret); + goto err; + } + + ret = of_clk_add_hw_provider(parent->of_node, of_clk_hw_simple_get, + &a53cc->clkr.hw); + if (ret) { + dev_err(dev, "failed to add clock provider: %d\n", ret); + goto err; + } + + platform_set_drvdata(pdev, a53cc); + + return 0; + +err: + clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb); + return ret; +} + +static int qcom_apcs_msm8916_clk_remove(struct platform_device *pdev) +{ + struct clk_regmap_mux_div *a53cc = platform_get_drvdata(pdev); + struct device *parent = pdev->dev.parent; + + clk_notifier_unregister(a53cc->pclk, &a53cc->clk_nb); + of_clk_del_provider(parent->of_node); + + return 0; +} + +static struct platform_driver qcom_apcs_msm8916_clk_driver = { + .probe = qcom_apcs_msm8916_clk_probe, + .remove = qcom_apcs_msm8916_clk_remove, + .driver = { + .name = "qcom-apcs-msm8916-clk", + }, +}; +module_platform_driver(qcom_apcs_msm8916_clk_driver); + +MODULE_AUTHOR("Georgi Djakov "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("Qualcomm MSM8916 APCS clock driver");