From patchwork Fri Dec 8 09:20:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 121135 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp421649qgn; Fri, 8 Dec 2017 01:23:08 -0800 (PST) X-Google-Smtp-Source: AGs4zMa5hWvG5Ozx+WcBmx2XlrGbQEQV/DlByRcchvdsqouw4MbijrQXa7shycgz5QAt5aqIY34B X-Received: by 10.99.64.68 with SMTP id n65mr28866040pga.312.1512724988293; Fri, 08 Dec 2017 01:23:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512724988; cv=none; d=google.com; s=arc-20160816; b=Zq3HnnQgolMyOWBawqRrtGFfT8nFacoTJBEDyq9O3ChJoO3UKGIOvUcRl33EVIwuxu /C0wB/LbF4ji/wq/qy6A0/x1+U9QP2hT8K6ZThGGpIc0DFujK2m+6Z3PIIQTX9DmXLZ2 zNGoI0QuFWsjf3FvC4+2c8G/cjEOzWWMRpwAxRMsYNVLTf/gEo02+OOkMoqicWYhp1oT fZ38C3XQ71Yyzg6v6ssg14pzqDJzWsiVfxcjoK7muezk136yljWkby9UVWK/unphMpC6 rQ3JZ8q452ptYpWqBGFOaQF4RXTJXsIbnm2BjInrxQ40nSkpabBt191zjZAk5a8ccngX egZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=rqjqzIy4V1lRvIFzp1ztyAUiffqtu3EETNBc5+iOPS0=; b=JQm7KTPwGLYsVcdL7TeddfuoMJCfaf7BCITqqe773/Brt3mmUmtuflH76xE4oEBVe2 /zEoro2vpb+8+KtvIxty0kkt1rbxIFfOM+QK4gIwrLBAeYfUyk8uROe+XKi7NM/e3748 XDNn9YbgzqA+Wx+zjIV+9odXFXZb8vnJLMuWpztUkrTVb5J1877EqfJsJcYsEgrU4o5M sKlXX8W+VqbL+SC/3Qa40GRKCr2+3DvnlLrPE2yvswAflxjcUrPmoHI6/g7k8T5YDMks +SnGkoUq7CZ+L1PNnp3jA9mnUYUm6FQG6FMbQvBWPLpKHU9M5CB9Gihlt0thdn/p0WjH 9/Mw== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NiqexMaq; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 7si5240252ple.17.2017.12.08.01.23.07; Fri, 08 Dec 2017 01:23:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=NiqexMaq; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752529AbdLHJXG (ORCPT + 10 others); Fri, 8 Dec 2017 04:23:06 -0500 Received: from mail-wm0-f66.google.com ([74.125.82.66]:41323 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752495AbdLHJXE (ORCPT ); Fri, 8 Dec 2017 04:23:04 -0500 Received: by mail-wm0-f66.google.com with SMTP id g75so2273399wme.0 for ; Fri, 08 Dec 2017 01:23:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=IT9l0qhS/t3jtZz4E9gIzBXPHLpp/hrKXN+Fiq3747w=; b=NiqexMaqFWGs+02HI7mJUv0uiGl2fDbJjYmsx68ta5ZqO94gymdPILTwja9fSul1lh 5OroXOzrW4ORq4FexknS0oavQ7q7Yyi60kLrkdvh4YvNUYeeMYi2DYW4Qdgx16+DQ0bx VG8yxXd4atrU+g+Z7tE4sQNcJ9aZ+ebn40RLg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=IT9l0qhS/t3jtZz4E9gIzBXPHLpp/hrKXN+Fiq3747w=; b=fZC9TyIVubx/vedA43JtC9Ogu5VhalCTSqhh4xyTNGhmf7KTc3GC1PeUW59JnSO2pg lRi1mP5TNpOmN4NveMT40Zu1HM7M13swR0PBNk+Ur+Vir/FcCh4BuTLKrrpHM2AOVepX BjLHITYZ8bv4dQxZkYpNYsB1LyepQ3OczvG1sVXymNm2nfw3/lLkBq3kvUxvTPg14lRa KZSrPdO/JxZbnE3dwUZZqHLG2uvfpvEM6ggiPSS4/ljMGvV/nl6nJsET6ej6l3TJ9S5Q dhJqrP/CziHxXuQjaGHynap6ZNBNLKzchB+OKopXLHPxj77AmC/8q7PABu10WWk/0ine CuRA== X-Gm-Message-State: AKGB3mLrrB6yITUwrMMmHoJgMf/D49d6YjUB3Gz5omnziUJCraD0xJX4 RKd9tFNrP4XIJKAAzVau/1jzKA== X-Received: by 10.28.122.18 with SMTP id v18mr3962993wmc.3.1512724983356; Fri, 08 Dec 2017 01:23:03 -0800 (PST) Received: from localhost.localdomain (cpc90716-aztw32-2-0-cust92.18-1.cable.virginm.net. [86.26.100.93]) by smtp.gmail.com with ESMTPSA id y89sm1148740wmh.0.2017.12.08.01.23.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 08 Dec 2017 01:23:02 -0800 (PST) From: srinivas.kandagatla@linaro.org To: stanimir.varbanov@linaro.org, Stanimir Varbanov , linux-pci@vger.kernel.org, bhelgaas@google.com Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, robh+dt@kernel.org, devicetree@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH] PCI: qcom: add missing supplies required for msm8996 Date: Fri, 8 Dec 2017 09:20:53 +0000 Message-Id: <20171208092053.4417-1-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.15.0 Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Srinivas Kandagatla This patch adds supplies that are required for msm8996. Two of them vdda and vdda-1p8 are analog supplies that go in to controller, and the rest of the two vddpe's are supplies to PCIe endpoints. Without these supplies PCIe endpoints which require power supplies are not enumerated at all, as there is no one to power it up. Signed-off-by: Srinivas Kandagatla --- .../devicetree/bindings/pci/qcom,pcie.txt | 16 +++++++++++++ drivers/pci/dwc/pcie-qcom.c | 28 ++++++++++++++++++++-- 2 files changed, 42 insertions(+), 2 deletions(-) -- 2.15.0 -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt index 3c9d321b3d3b..045102cb3e12 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt @@ -179,6 +179,11 @@ Value type: Definition: A phandle to the core analog power supply +- vdda-1p8-supply: + Usage: required for msm8996 + Value type: + Definition: A phandle to the 1.8v analog power supply + - vdda_phy-supply: Usage: required for ipq/apq8064 Value type: @@ -189,6 +194,15 @@ Value type: Definition: A phandle to the analog power supply for IC which generates reference clock +- vddpe-supply: + Usage: optional + Value type: + Definition: A phandle to the PCIe endpoint power supply + +- vddpe1-supply: + Usage: optional + Value type: + Definition: A phandle to the PCIe endpoint power supply 1 - phys: Usage: required for apq8084 @@ -205,6 +219,8 @@ Value type: Definition: List of phandle and GPIO specifier pairs. Should contain - "perst-gpios" PCIe endpoint reset signal line + - "pe_en-gpios" PCIe endpoint enable signal line + - "pe_en1-gpios" PCIe endpoint enable1 signal line - "wake-gpios" PCIe endpoint wake signal line * Example for ipq/apq8064 diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c index 952a4fc4bf3c..01488f90da31 100644 --- a/drivers/pci/dwc/pcie-qcom.c +++ b/drivers/pci/dwc/pcie-qcom.c @@ -109,13 +109,15 @@ struct qcom_pcie_resources_1_0_0 { struct reset_control *core; struct regulator *vdda; }; - +#define QCOM_PCIE_MAX_SUPPLY 4 struct qcom_pcie_resources_2_3_2 { struct clk *aux_clk; struct clk *master_clk; struct clk *slave_clk; struct clk *cfg_clk; struct clk *pipe_clk; + int num_supplies; + struct regulator_bulk_data supplies[QCOM_PCIE_MAX_SUPPLY]; }; struct qcom_pcie_resources_2_4_0 { @@ -529,6 +531,17 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + int ret; + + res->supplies[0].supply = "vdda"; + res->supplies[1].supply = "vdda-1p8"; + res->supplies[2].supply = "vddpe"; + res->supplies[3].supply = "vddpe1"; + res->num_supplies = QCOM_PCIE_MAX_SUPPLY; + ret = devm_regulator_bulk_get(dev, QCOM_PCIE_MAX_SUPPLY, + res->supplies); + if (ret) + return ret; res->aux_clk = devm_clk_get(dev, "aux"); if (IS_ERR(res->aux_clk)) @@ -558,6 +571,8 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) clk_disable_unprepare(res->master_clk); clk_disable_unprepare(res->cfg_clk); clk_disable_unprepare(res->aux_clk); + + regulator_bulk_disable(res->num_supplies, res->supplies); } static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie) @@ -575,10 +590,16 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) u32 val; int ret; + ret = regulator_bulk_enable(res->num_supplies, res->supplies); + if (ret < 0) { + dev_err(dev, "cannot enable regulators\n"); + return ret; + } + ret = clk_prepare_enable(res->aux_clk); if (ret) { dev_err(dev, "cannot prepare/enable aux clock\n"); - return ret; + goto err_aux_clk; } ret = clk_prepare_enable(res->cfg_clk); @@ -629,6 +650,9 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) err_cfg_clk: clk_disable_unprepare(res->aux_clk); +err_aux_clk: + regulator_bulk_disable(res->num_supplies, res->supplies); + return ret; }