| Message ID | 20171208173128.28485-3-ard.biesheuvel@linaro.org |
|---|---|
| State | Accepted |
| Commit | 27f9f3496810f82d7be7dcee2f0a4bbf9d4b0322 |
| Headers | show |
| Series | ArmPlatformPkg: refactor LcdGraphicsOutputDxe driver | expand |
On Fri, Dec 08, 2017 at 05:31:25PM +0000, Ard Biesheuvel wrote: > Convert the PL111 specific code of LcdGraphicsOutputDxe into a LcdHwlib > implementation that we will wire up later into LcdGraphicsOutputDxe. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Girish Pathak <girish.pathak@arm.com> > Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> > Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> There are some whitespace and line length issues below, but no real howlers, and I guess it's all from existing code? Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> > --- > ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c | 126 +++++++++++++++++ > ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h | 149 ++++++++++++++++++++ > ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf | 40 ++++++ > 3 files changed, 315 insertions(+) > > diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c > new file mode 100644 > index 000000000000..9b4a02045ab7 > --- /dev/null > +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c > @@ -0,0 +1,126 @@ > +/** @file PL111Lcd.c > + > + Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR> > + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > +#include <Library/DebugLib.h> > +#include <Library/IoLib.h> > +#include <Library/LcdHwLib.h> > +#include <Library/LcdPlatformLib.h> > +#include <Library/MemoryAllocationLib.h> > + > +#include "PL111Lcd.h" > + > +/********************************************************************** > + * > + * This file contains all the bits of the PL111 that are > + * platform independent. > + * > + **********************************************************************/ > + > +EFI_STATUS > +LcdIdentify ( > + VOID > + ) > +{ > + DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL111\n", > + PL111_REG_CLCD_PERIPH_ID_0)); > + > + // Check if this is a PL111 > + if (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) == PL111_CLCD_PERIPH_ID_0 && > + MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) == PL111_CLCD_PERIPH_ID_1 && > + (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) == PL111_CLCD_PERIPH_ID_2 && > + MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) == PL111_CLCD_PERIPH_ID_3 && > + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) == PL111_CLCD_P_CELL_ID_0 && > + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) == PL111_CLCD_P_CELL_ID_1 && > + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) == PL111_CLCD_P_CELL_ID_2 && > + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) == PL111_CLCD_P_CELL_ID_3) { > + return EFI_SUCCESS; > + } > + return EFI_NOT_FOUND; > +} > + > +EFI_STATUS > +LcdInitialize ( > + IN EFI_PHYSICAL_ADDRESS VramBaseAddress > + ) > +{ > + // Define start of the VRAM. This never changes for any graphics mode > + MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress); > + MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer > + > + // Disable all interrupts from the PL111 > + MmioWrite32(PL111_REG_LCD_IMSC, 0); > + > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +LcdSetMode ( > + IN UINT32 ModeNumber > + ) > +{ > + EFI_STATUS Status; > + UINT32 HRes; > + UINT32 HSync; > + UINT32 HBackPorch; > + UINT32 HFrontPorch; > + UINT32 VRes; > + UINT32 VSync; > + UINT32 VBackPorch; > + UINT32 VFrontPorch; > + UINT32 LcdControl; > + LCD_BPP LcdBpp; > + > + // Set the video mode timings and other relevant information > + Status = LcdPlatformGetTimings (ModeNumber, > + &HRes,&HSync,&HBackPorch,&HFrontPorch, > + &VRes,&VSync,&VBackPorch,&VFrontPorch); > + ASSERT_EFI_ERROR (Status); > + if (EFI_ERROR( Status )) { > + return EFI_DEVICE_ERROR; > + } > + > + Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp); > + ASSERT_EFI_ERROR (Status); > + if (EFI_ERROR( Status )) { > + return EFI_DEVICE_ERROR; > + } > + > + // Disable the CLCD_LcdEn bit > + LcdControl = MmioRead32( PL111_REG_LCD_CONTROL); > + MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl & ~1); > + > + // Set Timings > + MmioWrite32 (PL111_REG_LCD_TIMING_0, HOR_AXIS_PANEL(HBackPorch, HFrontPorch, HSync, HRes)); > + MmioWrite32 (PL111_REG_LCD_TIMING_1, VER_AXIS_PANEL(VBackPorch, VFrontPorch, VSync, VRes)); > + MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY(HRes)); > + MmioWrite32 (PL111_REG_LCD_TIMING_3, 0); > + > + // PL111_REG_LCD_CONTROL > + LcdControl = PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP(LcdBpp) | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR; > + MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); > + > + // Turn on power to the LCD Panel > + LcdControl |= PL111_CTRL_LCD_PWR; > + MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); > + > + return EFI_SUCCESS; > +} > + > +VOID > +LcdShutdown ( > + VOID > + ) > +{ > + // Disable the controller > + MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN); > +} > diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h > new file mode 100644 > index 000000000000..18e28af805f6 > --- /dev/null > +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h > @@ -0,0 +1,149 @@ > +/** @file PL111Lcd.h > + > + Copyright (c) 2011, ARM Ltd. All rights reserved.<BR> > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > + **/ > + > +#ifndef _PL111LCD_H__ > +#define _PL111LCD_H__ > + > +/********************************************************************** > + * > + * This header file contains all the bits of the PL111 that are > + * platform independent. > + * > + **********************************************************************/ > + > +// Controller Register Offsets > +#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000) > +#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004) > +#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008) > +#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C) > +#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010) > +#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014) > +#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018) > +#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C) > +#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020) > +#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024) > +#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028) > +#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C) > +#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030) > +#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200) > + > +// Identification Register Offsets > +#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0) > +#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4) > +#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8) > +#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC) > +#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0) > +#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4) > +#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8) > +#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC) > + > +#define PL111_CLCD_PERIPH_ID_0 0x11 > +#define PL111_CLCD_PERIPH_ID_1 0x11 > +#define PL111_CLCD_PERIPH_ID_2 0x04 > +#define PL111_CLCD_PERIPH_ID_3 0x00 > +#define PL111_CLCD_P_CELL_ID_0 0x0D > +#define PL111_CLCD_P_CELL_ID_1 0xF0 > +#define PL111_CLCD_P_CELL_ID_2 0x05 > +#define PL111_CLCD_P_CELL_ID_3 0xB1 > + > +/**********************************************************************/ > + > +// Register components (register bits) > + > +// This should make life easier to program specific settings in the different registers > +// by simplifying the setting up of the individual bits of each register > +// and then assembling the final register value. > + > +/**********************************************************************/ > + > +// Register: PL111_REG_LCD_TIMING_0 > +#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2)) > + > +// Register: PL111_REG_LCD_TIMING_1 > +#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1)) > + > +// Register: PL111_REG_LCD_TIMING_2 > +#define PL111_BIT_SHIFT_PCD_HI 27 > +#define PL111_BIT_SHIFT_BCD 26 > +#define PL111_BIT_SHIFT_CPL 16 > +#define PL111_BIT_SHIFT_IOE 14 > +#define PL111_BIT_SHIFT_IPC 13 > +#define PL111_BIT_SHIFT_IHS 12 > +#define PL111_BIT_SHIFT_IVS 11 > +#define PL111_BIT_SHIFT_ACB 6 > +#define PL111_BIT_SHIFT_CLKSEL 5 > +#define PL111_BIT_SHIFT_PCD_LO 0 > + > +#define PL111_BCD (1 << 26) > +#define PL111_IPC (1 << 13) > +#define PL111_IHS (1 << 12) > +#define PL111_IVS (1 << 11) > + > +#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16)) > + > +// Register: PL111_REG_LCD_TIMING_3 > +#define PL111_BIT_SHIFT_LEE 16 > +#define PL111_BIT_SHIFT_LED 0 > + > +#define PL111_CTRL_WATERMARK (1 << 16) > +#define PL111_CTRL_LCD_V_COMP (1 << 12) > +#define PL111_CTRL_LCD_PWR (1 << 11) > +#define PL111_CTRL_BEPO (1 << 10) > +#define PL111_CTRL_BEBO (1 << 9) > +#define PL111_CTRL_BGR (1 << 8) > +#define PL111_CTRL_LCD_DUAL (1 << 7) > +#define PL111_CTRL_LCD_MONO_8 (1 << 6) > +#define PL111_CTRL_LCD_TFT (1 << 5) > +#define PL111_CTRL_LCD_BW (1 << 4) > +#define PL111_CTRL_LCD_1BPP (0 << 1) > +#define PL111_CTRL_LCD_2BPP (1 << 1) > +#define PL111_CTRL_LCD_4BPP (2 << 1) > +#define PL111_CTRL_LCD_8BPP (3 << 1) > +#define PL111_CTRL_LCD_16BPP (4 << 1) > +#define PL111_CTRL_LCD_24BPP (5 << 1) > +#define PL111_CTRL_LCD_16BPP_565 (6 << 1) > +#define PL111_CTRL_LCD_12BPP_444 (7 << 1) > +#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1) > +#define PL111_CTRL_LCD_EN 1 > + > +/**********************************************************************/ > + > +// Register: PL111_REG_LCD_TIMING_0 > +#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24) > +#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16) > +#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) > +#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2) > + > +// Register: PL111_REG_LCD_TIMING_1 > +#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24) > +#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16) > +#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10) > +#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC) > + > +// Register: PL111_REG_LCD_TIMING_2 > +#define PL111_BIT_MASK_PCD_HI 0xF8000000 > +#define PL111_BIT_MASK_BCD 0x04000000 > +#define PL111_BIT_MASK_CPL 0x03FF0000 > +#define PL111_BIT_MASK_IOE 0x00004000 > +#define PL111_BIT_MASK_IPC 0x00002000 > +#define PL111_BIT_MASK_IHS 0x00001000 > +#define PL111_BIT_MASK_IVS 0x00000800 > +#define PL111_BIT_MASK_ACB 0x000007C0 > +#define PL111_BIT_MASK_CLKSEL 0x00000020 > +#define PL111_BIT_MASK_PCD_LO 0x0000001F > + > +// Register: PL111_REG_LCD_TIMING_3 > +#define PL111_BIT_MASK_LEE 0x00010000 > +#define PL111_BIT_MASK_LED 0x0000007F > + > +#endif /* _PL111LCD_H__ */ > diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf > new file mode 100644 > index 000000000000..40db77eb079e > --- /dev/null > +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf > @@ -0,0 +1,40 @@ > +#/** @file PL111Lcd.inf > +# > +# Component description file for PL111Lcd module > +# > +# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.<BR> > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > +#**/ > + > +[Defines] > + INF_VERSION = 0x00010005 > + BASE_NAME = PL111Lcd > + FILE_GUID = 407B4008-BF5B-11DF-9547-CF16E0D72085 > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = LcdHwLib > + > +[Sources.common] > + PL111Lcd.c > + > +[Packages] > + ArmPlatformPkg/ArmPlatformPkg.dec > + ArmPkg/ArmPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + > +[LibraryClasses] > + UefiLib > + BaseLib > + DebugLib > + IoLib > + > +[FixedPcd] > + gArmPlatformTokenSpaceGuid.PcdPL111LcdBase > -- > 2.11.0 > _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
On 11 December 2017 at 17:39, Leif Lindholm <leif.lindholm@linaro.org> wrote: > On Fri, Dec 08, 2017 at 05:31:25PM +0000, Ard Biesheuvel wrote: >> Convert the PL111 specific code of LcdGraphicsOutputDxe into a LcdHwlib >> implementation that we will wire up later into LcdGraphicsOutputDxe. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Girish Pathak <girish.pathak@arm.com> >> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> >> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > > There are some whitespace and line length issues below, but no real > howlers, and I guess it's all from existing code? > Yeah. > Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> > Thanks. >> --- >> ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c | 126 +++++++++++++++++ >> ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h | 149 ++++++++++++++++++++ >> ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf | 40 ++++++ >> 3 files changed, 315 insertions(+) >> >> diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c >> new file mode 100644 >> index 000000000000..9b4a02045ab7 >> --- /dev/null >> +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c >> @@ -0,0 +1,126 @@ >> +/** @file PL111Lcd.c >> + >> + Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR> >> + >> + This program and the accompanying materials >> + are licensed and made available under the terms and conditions of the BSD License >> + which accompanies this distribution. The full text of the license may be found at >> + http://opensource.org/licenses/bsd-license.php >> + >> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. >> + >> +**/ >> +#include <Library/DebugLib.h> >> +#include <Library/IoLib.h> >> +#include <Library/LcdHwLib.h> >> +#include <Library/LcdPlatformLib.h> >> +#include <Library/MemoryAllocationLib.h> >> + >> +#include "PL111Lcd.h" >> + >> +/********************************************************************** >> + * >> + * This file contains all the bits of the PL111 that are >> + * platform independent. >> + * >> + **********************************************************************/ >> + >> +EFI_STATUS >> +LcdIdentify ( >> + VOID >> + ) >> +{ >> + DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL111\n", >> + PL111_REG_CLCD_PERIPH_ID_0)); >> + >> + // Check if this is a PL111 >> + if (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) == PL111_CLCD_PERIPH_ID_0 && >> + MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) == PL111_CLCD_PERIPH_ID_1 && >> + (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) == PL111_CLCD_PERIPH_ID_2 && >> + MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) == PL111_CLCD_PERIPH_ID_3 && >> + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) == PL111_CLCD_P_CELL_ID_0 && >> + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) == PL111_CLCD_P_CELL_ID_1 && >> + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) == PL111_CLCD_P_CELL_ID_2 && >> + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) == PL111_CLCD_P_CELL_ID_3) { >> + return EFI_SUCCESS; >> + } >> + return EFI_NOT_FOUND; >> +} >> + >> +EFI_STATUS >> +LcdInitialize ( >> + IN EFI_PHYSICAL_ADDRESS VramBaseAddress >> + ) >> +{ >> + // Define start of the VRAM. This never changes for any graphics mode >> + MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress); >> + MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer >> + >> + // Disable all interrupts from the PL111 >> + MmioWrite32(PL111_REG_LCD_IMSC, 0); >> + >> + return EFI_SUCCESS; >> +} >> + >> +EFI_STATUS >> +LcdSetMode ( >> + IN UINT32 ModeNumber >> + ) >> +{ >> + EFI_STATUS Status; >> + UINT32 HRes; >> + UINT32 HSync; >> + UINT32 HBackPorch; >> + UINT32 HFrontPorch; >> + UINT32 VRes; >> + UINT32 VSync; >> + UINT32 VBackPorch; >> + UINT32 VFrontPorch; >> + UINT32 LcdControl; >> + LCD_BPP LcdBpp; >> + >> + // Set the video mode timings and other relevant information >> + Status = LcdPlatformGetTimings (ModeNumber, >> + &HRes,&HSync,&HBackPorch,&HFrontPorch, >> + &VRes,&VSync,&VBackPorch,&VFrontPorch); >> + ASSERT_EFI_ERROR (Status); >> + if (EFI_ERROR( Status )) { >> + return EFI_DEVICE_ERROR; >> + } >> + >> + Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp); >> + ASSERT_EFI_ERROR (Status); >> + if (EFI_ERROR( Status )) { >> + return EFI_DEVICE_ERROR; >> + } >> + >> + // Disable the CLCD_LcdEn bit >> + LcdControl = MmioRead32( PL111_REG_LCD_CONTROL); >> + MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl & ~1); >> + >> + // Set Timings >> + MmioWrite32 (PL111_REG_LCD_TIMING_0, HOR_AXIS_PANEL(HBackPorch, HFrontPorch, HSync, HRes)); >> + MmioWrite32 (PL111_REG_LCD_TIMING_1, VER_AXIS_PANEL(VBackPorch, VFrontPorch, VSync, VRes)); >> + MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY(HRes)); >> + MmioWrite32 (PL111_REG_LCD_TIMING_3, 0); >> + >> + // PL111_REG_LCD_CONTROL >> + LcdControl = PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP(LcdBpp) | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR; >> + MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); >> + >> + // Turn on power to the LCD Panel >> + LcdControl |= PL111_CTRL_LCD_PWR; >> + MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); >> + >> + return EFI_SUCCESS; >> +} >> + >> +VOID >> +LcdShutdown ( >> + VOID >> + ) >> +{ >> + // Disable the controller >> + MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN); >> +} >> diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h >> new file mode 100644 >> index 000000000000..18e28af805f6 >> --- /dev/null >> +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h >> @@ -0,0 +1,149 @@ >> +/** @file PL111Lcd.h >> + >> + Copyright (c) 2011, ARM Ltd. All rights reserved.<BR> >> + This program and the accompanying materials >> + are licensed and made available under the terms and conditions of the BSD License >> + which accompanies this distribution. The full text of the license may be found at >> + http://opensource.org/licenses/bsd-license.php >> + >> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. >> + >> + **/ >> + >> +#ifndef _PL111LCD_H__ >> +#define _PL111LCD_H__ >> + >> +/********************************************************************** >> + * >> + * This header file contains all the bits of the PL111 that are >> + * platform independent. >> + * >> + **********************************************************************/ >> + >> +// Controller Register Offsets >> +#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000) >> +#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004) >> +#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008) >> +#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C) >> +#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010) >> +#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014) >> +#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018) >> +#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C) >> +#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020) >> +#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024) >> +#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028) >> +#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C) >> +#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030) >> +#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200) >> + >> +// Identification Register Offsets >> +#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0) >> +#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4) >> +#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8) >> +#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC) >> +#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0) >> +#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4) >> +#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8) >> +#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC) >> + >> +#define PL111_CLCD_PERIPH_ID_0 0x11 >> +#define PL111_CLCD_PERIPH_ID_1 0x11 >> +#define PL111_CLCD_PERIPH_ID_2 0x04 >> +#define PL111_CLCD_PERIPH_ID_3 0x00 >> +#define PL111_CLCD_P_CELL_ID_0 0x0D >> +#define PL111_CLCD_P_CELL_ID_1 0xF0 >> +#define PL111_CLCD_P_CELL_ID_2 0x05 >> +#define PL111_CLCD_P_CELL_ID_3 0xB1 >> + >> +/**********************************************************************/ >> + >> +// Register components (register bits) >> + >> +// This should make life easier to program specific settings in the different registers >> +// by simplifying the setting up of the individual bits of each register >> +// and then assembling the final register value. >> + >> +/**********************************************************************/ >> + >> +// Register: PL111_REG_LCD_TIMING_0 >> +#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2)) >> + >> +// Register: PL111_REG_LCD_TIMING_1 >> +#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1)) >> + >> +// Register: PL111_REG_LCD_TIMING_2 >> +#define PL111_BIT_SHIFT_PCD_HI 27 >> +#define PL111_BIT_SHIFT_BCD 26 >> +#define PL111_BIT_SHIFT_CPL 16 >> +#define PL111_BIT_SHIFT_IOE 14 >> +#define PL111_BIT_SHIFT_IPC 13 >> +#define PL111_BIT_SHIFT_IHS 12 >> +#define PL111_BIT_SHIFT_IVS 11 >> +#define PL111_BIT_SHIFT_ACB 6 >> +#define PL111_BIT_SHIFT_CLKSEL 5 >> +#define PL111_BIT_SHIFT_PCD_LO 0 >> + >> +#define PL111_BCD (1 << 26) >> +#define PL111_IPC (1 << 13) >> +#define PL111_IHS (1 << 12) >> +#define PL111_IVS (1 << 11) >> + >> +#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16)) >> + >> +// Register: PL111_REG_LCD_TIMING_3 >> +#define PL111_BIT_SHIFT_LEE 16 >> +#define PL111_BIT_SHIFT_LED 0 >> + >> +#define PL111_CTRL_WATERMARK (1 << 16) >> +#define PL111_CTRL_LCD_V_COMP (1 << 12) >> +#define PL111_CTRL_LCD_PWR (1 << 11) >> +#define PL111_CTRL_BEPO (1 << 10) >> +#define PL111_CTRL_BEBO (1 << 9) >> +#define PL111_CTRL_BGR (1 << 8) >> +#define PL111_CTRL_LCD_DUAL (1 << 7) >> +#define PL111_CTRL_LCD_MONO_8 (1 << 6) >> +#define PL111_CTRL_LCD_TFT (1 << 5) >> +#define PL111_CTRL_LCD_BW (1 << 4) >> +#define PL111_CTRL_LCD_1BPP (0 << 1) >> +#define PL111_CTRL_LCD_2BPP (1 << 1) >> +#define PL111_CTRL_LCD_4BPP (2 << 1) >> +#define PL111_CTRL_LCD_8BPP (3 << 1) >> +#define PL111_CTRL_LCD_16BPP (4 << 1) >> +#define PL111_CTRL_LCD_24BPP (5 << 1) >> +#define PL111_CTRL_LCD_16BPP_565 (6 << 1) >> +#define PL111_CTRL_LCD_12BPP_444 (7 << 1) >> +#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1) >> +#define PL111_CTRL_LCD_EN 1 >> + >> +/**********************************************************************/ >> + >> +// Register: PL111_REG_LCD_TIMING_0 >> +#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24) >> +#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16) >> +#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) >> +#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2) >> + >> +// Register: PL111_REG_LCD_TIMING_1 >> +#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24) >> +#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16) >> +#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10) >> +#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC) >> + >> +// Register: PL111_REG_LCD_TIMING_2 >> +#define PL111_BIT_MASK_PCD_HI 0xF8000000 >> +#define PL111_BIT_MASK_BCD 0x04000000 >> +#define PL111_BIT_MASK_CPL 0x03FF0000 >> +#define PL111_BIT_MASK_IOE 0x00004000 >> +#define PL111_BIT_MASK_IPC 0x00002000 >> +#define PL111_BIT_MASK_IHS 0x00001000 >> +#define PL111_BIT_MASK_IVS 0x00000800 >> +#define PL111_BIT_MASK_ACB 0x000007C0 >> +#define PL111_BIT_MASK_CLKSEL 0x00000020 >> +#define PL111_BIT_MASK_PCD_LO 0x0000001F >> + >> +// Register: PL111_REG_LCD_TIMING_3 >> +#define PL111_BIT_MASK_LEE 0x00010000 >> +#define PL111_BIT_MASK_LED 0x0000007F >> + >> +#endif /* _PL111LCD_H__ */ >> diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf >> new file mode 100644 >> index 000000000000..40db77eb079e >> --- /dev/null >> +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf >> @@ -0,0 +1,40 @@ >> +#/** @file PL111Lcd.inf >> +# >> +# Component description file for PL111Lcd module >> +# >> +# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.<BR> >> +# This program and the accompanying materials >> +# are licensed and made available under the terms and conditions of the BSD License >> +# which accompanies this distribution. The full text of the license may be found at >> +# http://opensource.org/licenses/bsd-license.php >> +# >> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, >> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. >> +# >> +#**/ >> + >> +[Defines] >> + INF_VERSION = 0x00010005 >> + BASE_NAME = PL111Lcd >> + FILE_GUID = 407B4008-BF5B-11DF-9547-CF16E0D72085 >> + MODULE_TYPE = BASE >> + VERSION_STRING = 1.0 >> + LIBRARY_CLASS = LcdHwLib >> + >> +[Sources.common] >> + PL111Lcd.c >> + >> +[Packages] >> + ArmPlatformPkg/ArmPlatformPkg.dec >> + ArmPkg/ArmPkg.dec >> + MdeModulePkg/MdeModulePkg.dec >> + MdePkg/MdePkg.dec >> + >> +[LibraryClasses] >> + UefiLib >> + BaseLib >> + DebugLib >> + IoLib >> + >> +[FixedPcd] >> + gArmPlatformTokenSpaceGuid.PcdPL111LcdBase >> -- >> 2.11.0 >> _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel
diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c new file mode 100644 index 000000000000..9b4a02045ab7 --- /dev/null +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.c @@ -0,0 +1,126 @@ +/** @file PL111Lcd.c + + Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR> + + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/LcdHwLib.h> +#include <Library/LcdPlatformLib.h> +#include <Library/MemoryAllocationLib.h> + +#include "PL111Lcd.h" + +/********************************************************************** + * + * This file contains all the bits of the PL111 that are + * platform independent. + * + **********************************************************************/ + +EFI_STATUS +LcdIdentify ( + VOID + ) +{ + DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL111\n", + PL111_REG_CLCD_PERIPH_ID_0)); + + // Check if this is a PL111 + if (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) == PL111_CLCD_PERIPH_ID_0 && + MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) == PL111_CLCD_PERIPH_ID_1 && + (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) == PL111_CLCD_PERIPH_ID_2 && + MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) == PL111_CLCD_PERIPH_ID_3 && + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) == PL111_CLCD_P_CELL_ID_0 && + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) == PL111_CLCD_P_CELL_ID_1 && + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) == PL111_CLCD_P_CELL_ID_2 && + MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) == PL111_CLCD_P_CELL_ID_3) { + return EFI_SUCCESS; + } + return EFI_NOT_FOUND; +} + +EFI_STATUS +LcdInitialize ( + IN EFI_PHYSICAL_ADDRESS VramBaseAddress + ) +{ + // Define start of the VRAM. This never changes for any graphics mode + MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress); + MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer + + // Disable all interrupts from the PL111 + MmioWrite32(PL111_REG_LCD_IMSC, 0); + + return EFI_SUCCESS; +} + +EFI_STATUS +LcdSetMode ( + IN UINT32 ModeNumber + ) +{ + EFI_STATUS Status; + UINT32 HRes; + UINT32 HSync; + UINT32 HBackPorch; + UINT32 HFrontPorch; + UINT32 VRes; + UINT32 VSync; + UINT32 VBackPorch; + UINT32 VFrontPorch; + UINT32 LcdControl; + LCD_BPP LcdBpp; + + // Set the video mode timings and other relevant information + Status = LcdPlatformGetTimings (ModeNumber, + &HRes,&HSync,&HBackPorch,&HFrontPorch, + &VRes,&VSync,&VBackPorch,&VFrontPorch); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR( Status )) { + return EFI_DEVICE_ERROR; + } + + Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR( Status )) { + return EFI_DEVICE_ERROR; + } + + // Disable the CLCD_LcdEn bit + LcdControl = MmioRead32( PL111_REG_LCD_CONTROL); + MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl & ~1); + + // Set Timings + MmioWrite32 (PL111_REG_LCD_TIMING_0, HOR_AXIS_PANEL(HBackPorch, HFrontPorch, HSync, HRes)); + MmioWrite32 (PL111_REG_LCD_TIMING_1, VER_AXIS_PANEL(VBackPorch, VFrontPorch, VSync, VRes)); + MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY(HRes)); + MmioWrite32 (PL111_REG_LCD_TIMING_3, 0); + + // PL111_REG_LCD_CONTROL + LcdControl = PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP(LcdBpp) | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR; + MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); + + // Turn on power to the LCD Panel + LcdControl |= PL111_CTRL_LCD_PWR; + MmioWrite32(PL111_REG_LCD_CONTROL, LcdControl); + + return EFI_SUCCESS; +} + +VOID +LcdShutdown ( + VOID + ) +{ + // Disable the controller + MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN); +} diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h new file mode 100644 index 000000000000..18e28af805f6 --- /dev/null +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.h @@ -0,0 +1,149 @@ +/** @file PL111Lcd.h + + Copyright (c) 2011, ARM Ltd. All rights reserved.<BR> + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + **/ + +#ifndef _PL111LCD_H__ +#define _PL111LCD_H__ + +/********************************************************************** + * + * This header file contains all the bits of the PL111 that are + * platform independent. + * + **********************************************************************/ + +// Controller Register Offsets +#define PL111_REG_LCD_TIMING_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000) +#define PL111_REG_LCD_TIMING_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004) +#define PL111_REG_LCD_TIMING_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008) +#define PL111_REG_LCD_TIMING_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C) +#define PL111_REG_LCD_UP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010) +#define PL111_REG_LCD_LP_BASE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014) +#define PL111_REG_LCD_CONTROL ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018) +#define PL111_REG_LCD_IMSC ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C) +#define PL111_REG_LCD_RIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020) +#define PL111_REG_LCD_MIS ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024) +#define PL111_REG_LCD_ICR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028) +#define PL111_REG_LCD_UP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C) +#define PL111_REG_LCD_LP_CURR ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030) +#define PL111_REG_LCD_PALETTE ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200) + +// Identification Register Offsets +#define PL111_REG_CLCD_PERIPH_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0) +#define PL111_REG_CLCD_PERIPH_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4) +#define PL111_REG_CLCD_PERIPH_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8) +#define PL111_REG_CLCD_PERIPH_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC) +#define PL111_REG_CLCD_P_CELL_ID_0 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0) +#define PL111_REG_CLCD_P_CELL_ID_1 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4) +#define PL111_REG_CLCD_P_CELL_ID_2 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8) +#define PL111_REG_CLCD_P_CELL_ID_3 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC) + +#define PL111_CLCD_PERIPH_ID_0 0x11 +#define PL111_CLCD_PERIPH_ID_1 0x11 +#define PL111_CLCD_PERIPH_ID_2 0x04 +#define PL111_CLCD_PERIPH_ID_3 0x00 +#define PL111_CLCD_P_CELL_ID_0 0x0D +#define PL111_CLCD_P_CELL_ID_1 0xF0 +#define PL111_CLCD_P_CELL_ID_2 0x05 +#define PL111_CLCD_P_CELL_ID_3 0xB1 + +/**********************************************************************/ + +// Register components (register bits) + +// This should make life easier to program specific settings in the different registers +// by simplifying the setting up of the individual bits of each register +// and then assembling the final register value. + +/**********************************************************************/ + +// Register: PL111_REG_LCD_TIMING_0 +#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2)) + +// Register: PL111_REG_LCD_TIMING_1 +#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1)) + +// Register: PL111_REG_LCD_TIMING_2 +#define PL111_BIT_SHIFT_PCD_HI 27 +#define PL111_BIT_SHIFT_BCD 26 +#define PL111_BIT_SHIFT_CPL 16 +#define PL111_BIT_SHIFT_IOE 14 +#define PL111_BIT_SHIFT_IPC 13 +#define PL111_BIT_SHIFT_IHS 12 +#define PL111_BIT_SHIFT_IVS 11 +#define PL111_BIT_SHIFT_ACB 6 +#define PL111_BIT_SHIFT_CLKSEL 5 +#define PL111_BIT_SHIFT_PCD_LO 0 + +#define PL111_BCD (1 << 26) +#define PL111_IPC (1 << 13) +#define PL111_IHS (1 << 12) +#define PL111_IVS (1 << 11) + +#define CLK_SIG_POLARITY(hor_res) (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16)) + +// Register: PL111_REG_LCD_TIMING_3 +#define PL111_BIT_SHIFT_LEE 16 +#define PL111_BIT_SHIFT_LED 0 + +#define PL111_CTRL_WATERMARK (1 << 16) +#define PL111_CTRL_LCD_V_COMP (1 << 12) +#define PL111_CTRL_LCD_PWR (1 << 11) +#define PL111_CTRL_BEPO (1 << 10) +#define PL111_CTRL_BEBO (1 << 9) +#define PL111_CTRL_BGR (1 << 8) +#define PL111_CTRL_LCD_DUAL (1 << 7) +#define PL111_CTRL_LCD_MONO_8 (1 << 6) +#define PL111_CTRL_LCD_TFT (1 << 5) +#define PL111_CTRL_LCD_BW (1 << 4) +#define PL111_CTRL_LCD_1BPP (0 << 1) +#define PL111_CTRL_LCD_2BPP (1 << 1) +#define PL111_CTRL_LCD_4BPP (2 << 1) +#define PL111_CTRL_LCD_8BPP (3 << 1) +#define PL111_CTRL_LCD_16BPP (4 << 1) +#define PL111_CTRL_LCD_24BPP (5 << 1) +#define PL111_CTRL_LCD_16BPP_565 (6 << 1) +#define PL111_CTRL_LCD_12BPP_444 (7 << 1) +#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1) +#define PL111_CTRL_LCD_EN 1 + +/**********************************************************************/ + +// Register: PL111_REG_LCD_TIMING_0 +#define PL111_LCD_TIMING_0_HBP(hbp) (((hbp) & 0xFF) << 24) +#define PL111_LCD_TIMING_0_HFP(hfp) (((hfp) & 0xFF) << 16) +#define PL111_LCD_TIMING_0_HSW(hsw) (((hsw) & 0xFF) << 8) +#define PL111_LCD_TIMING_0_PPL(ppl) (((hsw) & 0x3F) << 2) + +// Register: PL111_REG_LCD_TIMING_1 +#define PL111_LCD_TIMING_1_VBP(vbp) (((vbp) & 0xFF) << 24) +#define PL111_LCD_TIMING_1_VFP(vfp) (((vfp) & 0xFF) << 16) +#define PL111_LCD_TIMING_1_VSW(vsw) (((vsw) & 0x3F) << 10) +#define PL111_LCD_TIMING_1_LPP(lpp) ((lpp) & 0xFC) + +// Register: PL111_REG_LCD_TIMING_2 +#define PL111_BIT_MASK_PCD_HI 0xF8000000 +#define PL111_BIT_MASK_BCD 0x04000000 +#define PL111_BIT_MASK_CPL 0x03FF0000 +#define PL111_BIT_MASK_IOE 0x00004000 +#define PL111_BIT_MASK_IPC 0x00002000 +#define PL111_BIT_MASK_IHS 0x00001000 +#define PL111_BIT_MASK_IVS 0x00000800 +#define PL111_BIT_MASK_ACB 0x000007C0 +#define PL111_BIT_MASK_CLKSEL 0x00000020 +#define PL111_BIT_MASK_PCD_LO 0x0000001F + +// Register: PL111_REG_LCD_TIMING_3 +#define PL111_BIT_MASK_LEE 0x00010000 +#define PL111_BIT_MASK_LED 0x0000007F + +#endif /* _PL111LCD_H__ */ diff --git a/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf new file mode 100644 index 000000000000..40db77eb079e --- /dev/null +++ b/ArmPlatformPkg/Library/PL111Lcd/PL111Lcd.inf @@ -0,0 +1,40 @@ +#/** @file PL111Lcd.inf +# +# Component description file for PL111Lcd module +# +# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.<BR> +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PL111Lcd + FILE_GUID = 407B4008-BF5B-11DF-9547-CF16E0D72085 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = LcdHwLib + +[Sources.common] + PL111Lcd.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiLib + BaseLib + DebugLib + IoLib + +[FixedPcd] + gArmPlatformTokenSpaceGuid.PcdPL111LcdBase