diff mbox series

[2/2] hw/intc/arm_gic: reserved register addresses are RAZ/WI

Message ID 1513183941-24300-3-git-send-email-peter.maydell@linaro.org
State Accepted
Commit 0cf09852015e47a5fbb974ff7ac320366afd21ee
Headers show
Series GICv2 & GICv3: RAZ/WI reserved addresses rather than aborting | expand

Commit Message

Peter Maydell Dec. 13, 2017, 4:52 p.m. UTC 
The GICv2 specification says that reserved register addresses
must RAZ/WI; now that we implement external abort handling
for Arm CPUs this means we must return MEMTX_OK rather than
MEMTX_ERROR, to avoid generating a spurious guest data abort.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---
 hw/intc/arm_gic.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

-- 
2.7.4

Comments

Alistair Francis Jan. 9, 2018, 9:41 p.m. UTC | #1 
On Wed, Dec 13, 2017 at 8:52 AM, Peter Maydell <peter.maydell@linaro.org> wrote:
> The GICv2 specification says that reserved register addresses

> must RAZ/WI; now that we implement external abort handling

> for Arm CPUs this means we must return MEMTX_OK rather than

> MEMTX_ERROR, to avoid generating a spurious guest data abort.

>

> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Looks good to me.

Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>


Alistair


> ---

>  hw/intc/arm_gic.c | 5 +++--

>  1 file changed, 3 insertions(+), 2 deletions(-)

>

> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c

> index 5a0e2a3..d701e49 100644

> --- a/hw/intc/arm_gic.c

> +++ b/hw/intc/arm_gic.c

> @@ -1261,7 +1261,8 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,

>      default:

>          qemu_log_mask(LOG_GUEST_ERROR,

>                        "gic_cpu_read: Bad offset %x\n", (int)offset);

> -        return MEMTX_ERROR;

> +        *data = 0;

> +        break;

>      }

>      return MEMTX_OK;

>  }

> @@ -1329,7 +1330,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,

>      default:

>          qemu_log_mask(LOG_GUEST_ERROR,

>                        "gic_cpu_write: Bad offset %x\n", (int)offset);

> -        return MEMTX_ERROR;

> +        return MEMTX_OK;

>      }

>      gic_update(s);

>      return MEMTX_OK;

> --

> 2.7.4

>

>
diff mbox series

Patch

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 5a0e2a3..d701e49 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -1261,7 +1261,8 @@  static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
     default:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "gic_cpu_read: Bad offset %x\n", (int)offset);
-        return MEMTX_ERROR;
+        *data = 0;
+        break;
     }
     return MEMTX_OK;
 }
@@ -1329,7 +1330,7 @@  static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
     default:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "gic_cpu_write: Bad offset %x\n", (int)offset);
-        return MEMTX_ERROR;
+        return MEMTX_OK;
     }
     gic_update(s);
     return MEMTX_OK;