From patchwork Thu Dec 14 16:09:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 121989 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp7006659qgn; Thu, 14 Dec 2017 08:12:02 -0800 (PST) X-Google-Smtp-Source: ACJfBosO0kFVizTx8JdfarXsInU3xpFK0SOpSp5b4q2nacgcNZP4tdO3eMUIjOh3czJFNCngm2AM X-Received: by 10.99.191.1 with SMTP id v1mr8914477pgf.93.1513267922544; Thu, 14 Dec 2017 08:12:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1513267922; cv=none; d=google.com; s=arc-20160816; b=OanhBAdA1URp313eS3nXW0qC9KBKRUz27Jjs1IZkS2cge7+twy6MLGYdTLdjQj1pS2 u87PJKjMgZ9qOm+x8dfXmRQm40D9YeRXP2FhVS7SPHgTFhbWzfLQypU+jwM6rY+D9de6 TFFqD+XdtFvhHvAG3lwzWtHeM6RXKwAAM3tXY0iWEaW+2PO2hme7RKhLdLRBk2heMh+O 1IOw87w0a+VFU0sWWKD8RfchvavPp88p51w+cDTwPSJcRNlOx7jcVEu8BGWTpC1MVunS EUG9wPHDu4d8QIrDzqiCeLTCagZK/3IrNq/HD3zRgyscJ1IUoocp8jowYRh/BpEpPFRZ GjcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:arc-authentication-results; bh=dK0oSAqnLwfPxBD8LBt6zVckXn360jSSdYR0ROKUTpw=; b=AcgIQVyVlLBxaCkHjgytZlv4yp4gz2O6PNc3biJhBWAylUl2JnHFHr7799nih+DFCV qtF2oo9tArcy4wuM5GL8QZFmv61lko4jzof7me2+hF1onrnorH8sSmFSzs/ju7ZPDqdi 2zwCXw5BPm5uIzZF00mJGsCb+LdE+fb+ZXjIIsQJLaEKW8T2fDFoJ2UW43Qi1uLqOvrG dX4EWeqTjjpAK3kbCCu59ttwyAKeJ7zmS+gjikFPMSReazHNjIfL0CNSFsKZYDxAvqkV qnnqfuy9uYT0i9jRpE2UuCxFNy0Ot92IHDPZ4kcjwMpNV5ANYhe8bTvXyTgm1M5HMQF6 75QA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w88si3480079pfj.200.2017.12.14.08.12.02; Thu, 14 Dec 2017 08:12:02 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753332AbdLNQMB (ORCPT + 6 others); Thu, 14 Dec 2017 11:12:01 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:60739 "EHLO huawei.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1753313AbdLNQL7 (ORCPT ); Thu, 14 Dec 2017 11:11:59 -0500 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 3000AAD778A73; Fri, 15 Dec 2017 00:11:43 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.202.227.237) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.361.1; Fri, 15 Dec 2017 00:11:35 +0800 From: Shameer Kolothum To: , , , CC: , , , , , , , , , Shameer Kolothum Subject: [PATCH v12 3/3] arm64:dts:hisilicon Disable hisilicon smmu node on hip06/hip07 Date: Thu, 14 Dec 2017 16:09:57 +0000 Message-ID: <20171214160957.13716-4-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 In-Reply-To: <20171214160957.13716-1-shameerali.kolothum.thodi@huawei.com> References: <20171214160957.13716-1-shameerali.kolothum.thodi@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.202.227.237] X-CFilter-Loop: Reflected Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms hip06/hip07 to support the SMMUv3 mappings for MSI transactions. PCIe controller on these platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This makes it difficult for these platforms to have SMMU translation for MSI. In order to workaround this, ARM SMMUv3 driver requires a quirk to treat the MSI regions separately. Such a quirk is currently missing for DT based systems and therefore we need to explicitly disable the hip06/hip07 smmu entries in dts. Signed-off-by: Shameer Kolothum Signed-off-by: Wei Xu --- arch/arm64/boot/dts/hisilicon/hip06.dtsi | 56 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/hisilicon/hip07.dtsi | 25 ++++++++++++++ 2 files changed, 81 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index a049b64..35202eb 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -291,6 +291,13 @@ #interrupt-cells = <2>; num-pins = <128>; }; + + mbigen_pcie0: intc_pcie0 { + msi-parent = <&its_dsa 0x40085>; + interrupt-controller; + #interrupt-cells = <2>; + num-pins = <10>; + }; }; mbigen_dsa@c0080000 { @@ -312,6 +319,31 @@ }; }; + /** + * HiSilicon erratum 161010801: This describes the limitation + * of HiSilicon platforms hip06/hip07 to support the SMMUv3 + * mappings for PCIe MSI transactions. + * PCIe controller on these platforms has to differentiate the + * MSI payload against other DMA payload and has to modify the + * MSI payload. This makes it difficult for these platforms to + * have a SMMU translation for MSI. In order to workaround this, + * ARM SMMUv3 driver requires a quirk to treat the MSI regions + * separately. Such a quirk is currently missing for DT based + * systems. Hence please make sure that the smmu pcie node on + * hip06 is disabled as this will break the PCIe functionality + * when iommu-map entry is used along with the PCIe node. + * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html + */ + smmu0: smmu_pcie { + compatible = "arm,smmu-v3"; + reg = <0x0 0xa0040000 0x0 0x20000>; + #iommu-cells = <1>; + dma-coherent; + smmu-cb-memtype = <0x0 0x1>; + hisilicon,broken-prefetch-cmd; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -676,6 +708,30 @@ <637 1>,<638 1>,<639 1>; status = "disabled"; }; + + pcie0: pcie@a0090000 { + compatible = "hisilicon,hip06-pcie-ecam"; + reg = <0 0xb0000000 0 0x2000000>, + <0 0xa0090000 0 0x10000>; + bus-range = <0 31>; + msi-map = <0x0000 &its_dsa 0x0000 0x2000>; + msi-map-mask = <0xffff>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + ranges = <0x02000000 0 0xb2000000 0x0 0xb2000000 0 + 0x5ff0000 0x01000000 0 0 0 0xb7ff0000 + 0 0x10000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0x0 0 0 1 &mbigen_pcie0 650 4 + 0x0 0 0 2 &mbigen_pcie0 650 4 + 0x0 0 0 3 &mbigen_pcie0 650 4 + 0x0 0 0 4 &mbigen_pcie0 650 4>; + status = "disabled"; + }; + }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 2c01a21..3e80bf3 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -1083,6 +1083,31 @@ }; }; + /** + * HiSilicon erratum 161010801: This describes the limitation + * of HiSilicon platforms hip06/hip07 to support the SMMUv3 + * mappings for PCIe MSI transactions. + * PCIe controller on these platforms has to differentiate the + * MSI payload against other DMA payload and has to modify the + * MSI payload. This makes it difficult for these platforms to + * have a SMMU translation for MSI. In order to workaround this, + * ARM SMMUv3 driver requires a quirk to treat the MSI regions + * separately. Such a quirk is currently missing for DT based + * systems. Hence please make sure that the smmu pcie node on + * hip07 is disabled as this will break the PCIe functionality + * when iommu-map entry is used along with the PCIe node. + * Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html + */ + smmu0: smmu_pcie { + compatible = "arm,smmu-v3"; + reg = <0x0 0xa0040000 0x0 0x20000>; + #iommu-cells = <1>; + dma-coherent; + smmu-cb-memtype = <0x0 0x1>; + hisilicon,broken-prefetch-cmd; + status = "disabled"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>;