| Message ID | 20171218172425.18200-8-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | ARM v8.1 simd + v8.3 complex insns | expand |
On 18 December 2017 at 17:24, Richard Henderson <richard.henderson@linaro.org> wrote: > Enable it for the "any" CPU used by *-linux-user. > > Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu.h | 1 + > linux-user/elfload.c | 1 + > target/arm/cpu.c | 1 + > target/arm/cpu64.c | 1 + > 4 files changed, 4 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index e047756b80..7a705a09a1 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1353,6 +1353,7 @@ enum arm_features { > ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ > ARM_FEATURE_V8_1_SIMD, /* has ARMv8.1-SIMD */ > ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ > + ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ This is a bit inconsistent. If we're going with the architectural feature names this is "ARMv8.3-CompNum", so ARM_FEATURE_V8_3_COMPNUM. If we're going with the ID_AA64ISARn_EL1 field names then ARM_FEATURE_V8_1_SIMD should be ARM_FEATURE_V8_RDM... > }; thanks -- PMM
On 01/15/2018 09:53 AM, Peter Maydell wrote: > On 18 December 2017 at 17:24, Richard Henderson > <richard.henderson@linaro.org> wrote: >> Enable it for the "any" CPU used by *-linux-user. >> >> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> >> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> >> --- >> target/arm/cpu.h | 1 + >> linux-user/elfload.c | 1 + >> target/arm/cpu.c | 1 + >> target/arm/cpu64.c | 1 + >> 4 files changed, 4 insertions(+) >> >> diff --git a/target/arm/cpu.h b/target/arm/cpu.h >> index e047756b80..7a705a09a1 100644 >> --- a/target/arm/cpu.h >> +++ b/target/arm/cpu.h >> @@ -1353,6 +1353,7 @@ enum arm_features { >> ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ >> ARM_FEATURE_V8_1_SIMD, /* has ARMv8.1-SIMD */ >> ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ >> + ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ > > This is a bit inconsistent. If we're going with the architectural > feature names this is "ARMv8.3-CompNum", so ARM_FEATURE_V8_3_COMPNUM. > If we're going with the ID_AA64ISARn_EL1 field names then > ARM_FEATURE_V8_1_SIMD should be ARM_FEATURE_V8_RDM... You preferred ASIMDRDM earlier. Does this mean you prefer V8_RDM? I hadn't noticed I was being inconsistent as to whence I drew my names. Gimme your preferred names and I'll use 'em. r~
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e047756b80..7a705a09a1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1353,6 +1353,7 @@ enum arm_features { ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ ARM_FEATURE_V8_1_SIMD, /* has ARMv8.1-SIMD */ ARM_FEATURE_V8_FP16, /* implements v8.2 half-precision float */ + ARM_FEATURE_V8_FCMA, /* has complex number part of v8.3 extensions. */ }; static inline int arm_feature(CPUARMState *env, int feature) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 95f550518e..e07184902f 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -541,6 +541,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2); GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32); GET_FEATURE(ARM_FEATURE_V8_1_SIMD, ARM_HWCAP_A64_ASIMDRDM); + GET_FEATURE(ARM_FEATURE_V8_FCMA, ARM_HWCAP_A64_FCMA); #undef GET_FEATURE return hwcaps; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index afe84645af..6cd8ae1459 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1629,6 +1629,7 @@ static void arm_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD); + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); cpu->midr = 0xffffffff; } #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 67a01bf7ce..43b42f95fd 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -228,6 +228,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_CRC); set_feature(&cpu->env, ARM_FEATURE_V8_1_SIMD); set_feature(&cpu->env, ARM_FEATURE_V8_FP16); + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ }