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Tue, 16 Oct 2012 20:03:48 +0900 (KST) Received: from hatim-linux.sisodomain.com ([107.108.73.95]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MBZ0099QFZTVV60@mmp1.samsung.com> for patches@linaro.org; Tue, 16 Oct 2012 20:03:48 +0900 (KST) From: Hatim Ali To: u-boot@lists.denx.de Cc: promsoft@gmail.com, patches@linaro.org, sjg@chromium.org Subject: [PATCH 1/6 V5] EXYNOS5: Add pinmux support for SPI Date: Tue, 16 Oct 2012 16:28:41 +0530 Message-id: <1350385126-19312-2-git-send-email-hatim.rv@samsung.com> X-Mailer: git-send-email 1.7.2.3 In-reply-to: <1350385126-19312-1-git-send-email-hatim.rv@samsung.com> References: <1350385126-19312-1-git-send-email-hatim.rv@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrDLMWRmVeSWpSXmKPExsWyRsSkWlfEvjbA4HuXosWUw19YHBg97lzb wxbAGMVlk5Kak1mWWqRvl8CVMf/IAcaCG+IVu/p2sjYwrhDuYuTkkBAwkTh3/DAbhC0mceHe eiCbi0NIYCmjxMvz95lgitrOdzBCJBYxSiyb/BXGYZJ4fW4pK0gVm4CaxPrXnWCjRAQkJH71 X2UEsZkFbCQ+X54MZgsLWEucu/QAzGYRUJW48/k0UC8HB6+Ai0TfrSKIZQoSr26sZQexOQVc JR6t6wArFwIqOXVxElSrgMS3yYdYQFolBGQlNh1gBjlHQuAym8TsCS2MEHMkJQ6uuMEygVF4 ASPDKkbR1ILkguKk9FxDveLE3OLSvHS95PzcTYzAIDz975nUDsaVDRaHGAU4GJV4eDOcawKE WBPLiitzDzFKcDArifCq2tYGCPGmJFZWpRblxxeV5qQWH2L0AbpkIrOUaHI+MELySuINjU3M TY1NLY2MzExNcQgrifM2e6QECAmkJ5akZqemFqQWwYxj4uCUamCUeNC9XnKJycxNJmnbTzru 0L135Gjyis+r42Q5rRcacMlt6bC5dor7nlTaBQ2db4ctbi8U0P6txGW8RemGRRDLbbOZ8jMy srs8wlTa8lyf/N/WdFzGQO290pXJ+Vwp3TPUH0+1uPz/vfC/4oAkMUMP47mplxj06jX0Xsw0 XORX1WXBGCjaPEuJpTgj0VCLuag4EQDbyYEabwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupmkeLIzCtJLcpLzFFi42I5/e+xgK6IfW2AwcHLQhZTDn9hcWD0uHNt D1sAY1QDo01GamJKapFCal5yfkpmXrqtkndwvHO8qZmBoa6hpYW5kkJeYm6qrZKLT4CuW2YO 0FglhbLEnFKgUEBicbGSvh2mCaEhbroWMI0Rur4hQXA9RgZoIGENY8b8IwcYC26IV+zq28na wLhCuIuRk0NCwESi7XwHI4QtJnHh3nq2LkYuDiGBRYwSyyZ/ZYRymCRen1vKClLFJqAmsf51 JxuILSIgIfGr/ypYN7OAjcTny5PBbGEBa4lzlx6A2SwCqhJ3Pp8G6uXg4BVwkei7VQSxTEHi 1Y217CA2p4CrxKN1EEcIAZWcujiJcQIj7wJGhlWMoqkFyQXFSem5hnrFibnFpXnpesn5uZsY wSH+TGoH48oGi0OMAhyMSjy8Gc41AUKsiWXFlbmHGCU4mJVEeFVtawOEeFMSK6tSi/Lji0pz UosPMfoAHTWRWUo0OR8Yf3kl8YbGJuamxqaWJhYmZpY4hJXEeZs9UgKEBNITS1KzU1MLUotg xjFxcEo1MCqLuT9nqGVaceReybUPganJP5fPXNjH7PJ1fo6BR1KXRZiV0+O96w7x3jsV/21D J8OsbVGm0WpJIeZKp2L2Szzb63PmuHz7+YP/DN72dmb9WHEp4YEI1/uAyJU7KxofsPx5US6i 7Xj0wUbTDS476kzmTVohddLxXE7FxjdedivnMZbPtH+3y0WJpTgj0VCLuag4EQDZH7bxngIA AA== X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQk8by3QX59TRQiXTgT+dntWye9Kl6D7X0pBsrt9Sw9IWKi/0xfWi0+PYuh7iKWVHrGAWaga From: Rajeshwari Shinde This patch adds pinmux support for SPI channels Signed-off-by: Rajeshwari Shinde Signed-off-by: Hatim Ali Acked-by: Simon Glass --- Changes since v4: Fixed minor nits suggested by Simon Glass arch/arm/cpu/armv7/exynos/pinmux.c | 51 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/periph.h | 5 +++ 2 files changed, 56 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 5796d56..e01bef4 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -112,6 +112,7 @@ static int exynos5_mmc_config(int peripheral, int flags) s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); } + return 0; } @@ -230,6 +231,49 @@ static void exynos5_i2c_config(int peripheral, int flags) } } +void exynos5_spi_config(int peripheral) +{ + int cfg = 0, pin = 0, i; + struct s5p_gpio_bank *bank = NULL; + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + struct exynos5_gpio_part2 *gpio2 = + (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); + + switch (peripheral) { + case PERIPH_ID_SPI0: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI1: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 4; + break; + case PERIPH_ID_SPI2: + bank = &gpio1->b1; + cfg = GPIO_FUNC(0x5); + pin = 1; + break; + case PERIPH_ID_SPI3: + bank = &gpio2->f1; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI4: + for (i = 2; i < 4; i++) + s5p_gpio_cfg_pin(&gpio2->f0, i, GPIO_FUNC(0x4)); + for (i = 4; i < 6; i++) + s5p_gpio_cfg_pin(&gpio2->e0, i, GPIO_FUNC(0x4)); + break; + } + if (peripheral != PERIPH_ID_SPI4) { + for (i = pin; i < pin + 4; i++) + s5p_gpio_cfg_pin(bank, i, cfg); + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -257,6 +301,13 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_I2C7: exynos5_i2c_config(peripheral, flags); break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + exynos5_spi_config(peripheral); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 082611c..4054fb6 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -44,6 +44,11 @@ enum periph_id { PERIPH_ID_SDMMC3, PERIPH_ID_SDMMC4, PERIPH_ID_SROMC, + PERIPH_ID_SPI0, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, PERIPH_ID_UART0, PERIPH_ID_UART1, PERIPH_ID_UART2,