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[81.169.180.215]) by mx.google.com with ESMTP id b8si897749edf.174.2017.12.27.04.37.01; Wed, 27 Dec 2017 04:37:01 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Lq4p+5ag; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 527DEC21DD0; Wed, 27 Dec 2017 12:36:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E3773C21E9B; Wed, 27 Dec 2017 12:33:07 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8C633C21C59; Wed, 27 Dec 2017 12:26:30 +0000 (UTC) Received: from mail-wm0-f67.google.com (mail-wm0-f67.google.com [74.125.82.67]) by lists.denx.de (Postfix) with ESMTPS id 1C96AC21C34 for ; Wed, 27 Dec 2017 12:26:30 +0000 (UTC) Received: by mail-wm0-f67.google.com with SMTP id n138so39128087wmg.2 for ; Wed, 27 Dec 2017 04:26:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ciosNNHqgrLXgpvl8kH6eRc7Z7NECl38lhljdl6wOXk=; b=Lq4p+5agibTN9FFk06NAxsezBVNyJIp+AzbLBVovtnY/u+p9Sx6OXRyD/oP4Vie+K0 IrtjF2vKPwlC9zTtRX/xaS2n3au9nj0BTzsjuSI/ePLDdhTp1bZlhagYKaGL1rNG9rvA tAoarZi0oeJnmcAx7A/H8iuTrVok+splp/5JM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ciosNNHqgrLXgpvl8kH6eRc7Z7NECl38lhljdl6wOXk=; b=uLAm4A4bDh71yCsdMe4iaeDJ0QyqFOIIRlIPZ+b1RiEUoP8GN/ozMKJoqvJzCZA51H GC3LYtonN4Oou0T5Qb4k1h5jPpfkqqKs90AEGheOcBSJsXtR+SiQn2s33wJB1I9Llszl ffoSYoHHTcObgP9N0DZ0BUSWZvl3TRElEoBirzaqosb4M6lf9hHRSpvvOUZn5LWWxEeI t7HW589kLT1Av5HapDBwoReOAAhqKauLtlOyT0Vj+gHK+sSiSwz7k4J55cb24to6MEWN ayl6psS0fXM3chMFFAFllKxBg/z1MZHBLkDHm1Ee26PHNpg7GgfjINtB+5bJ/9yxS/jR 5Dkw== X-Gm-Message-State: AKGB3mKQNmMkECTkCLqfT7CcNDCF85MFTBxH1R3k+GD9IJI83icIXVKR dCithcTFMlqbWbgRNt+ih6g51ohNn9g= X-Received: by 10.80.138.199 with SMTP id k7mr34942816edk.229.1514377589344; Wed, 27 Dec 2017 04:26:29 -0800 (PST) Received: from localhost.localdomain ([109.255.42.2]) by smtp.gmail.com with ESMTPSA id a5sm28388838edm.47.2017.12.27.04.26.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Dec 2017 04:26:28 -0800 (PST) From: Bryan O'Donoghue To: u-boot@lists.denx.de Date: Wed, 27 Dec 2017 12:25:52 +0000 Message-Id: <1514377566-28512-10-git-send-email-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1514377566-28512-1-git-send-email-bryan.odonoghue@linaro.org> References: <1514377566-28512-1-git-send-email-bryan.odonoghue@linaro.org> X-Mailman-Approved-At: Wed, 27 Dec 2017 12:32:58 +0000 Cc: Fabio Estevam Subject: [U-Boot] [PATCH 09/23] arm: imx: hab: Add IVT header definitions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The various i.MX BootROMs containing the High Assurance Boot (HAB) block rely on a data structure called the Image Vector Table (IVT) to describe to the BootROM where to locate various data-structures used by HAB during authentication. This patch adds a definition of the IVT header for use in later patches, where we will break the current incorrect dependence on fixed offsets in favour of an IVT described parsing of incoming binaries. Signed-off-by: Bryan O'Donoghue Cc: Stefano Babic Cc: Fabio Estevam Cc: Peng Fan Cc: Albert Aribaud Cc: Sven Ebenfeld Cc: George McCollister --- arch/arm/include/asm/mach-imx/hab.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h index b2a8031..28cde38 100644 --- a/arch/arm/include/asm/mach-imx/hab.h +++ b/arch/arm/include/asm/mach-imx/hab.h @@ -10,6 +10,34 @@ #include +/* + * IVT header definitions + * Security Reference Manual for i.MX 7Dual and 7Solo Applications Processors, + * Rev. 0, 03/2017 + * Section : 6.7.1.1 + */ +#define IVT_HEADER_MAGIC 0xD1 +#define IVT_TOTAL_LENGTH 0x20 +#define IVT_HEADER_V1 0x40 +#define IVT_HEADER_V2 0x41 + +struct ivt_header { + uint8_t magic; + uint16_t length; + uint8_t version; +} __attribute__((packed)); + +struct ivt { + struct ivt_header hdr; /* IVT header above */ + uint32_t entry; /* Absolute address of first instruction */ + uint32_t reserved1; /* Reserved should be zero */ + uint32_t dcd; /* Absolute address of the image DCD */ + uint32_t boot; /* Absolute address of the boot data */ + uint32_t self; /* Absolute address of the IVT */ + uint32_t csf; /* Absolute address of the CSF */ + uint32_t reserved2; /* Reserved should be zero */ +}; + /* -------- start of HAB API updates ------------*/ /* The following are taken from HAB4 SIS */