[[PATCH,v2] 3/8] sunxi: Fix USB PHY index for H3/H5/A64

Message ID 1515168960-18960-4-git-send-email-jun.nie@linaro.org
State New
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  • [[PATCH,v2] 3/8] sunxi: Fix USB PHY index for H3/H5/A64
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Commit Message

Jun Nie Jan. 5, 2018, 4:15 p.m.
From: Chen-Yu Tsai <wens@csie.org>

On the new chips such as H3, H5, and A64, the USB OTG controller is
paired with a set of proper EHCI/OHCI USB hosts. To enable these hosts,
the USB PHY index count has to be reworked to start from this pair.

This patch reworks the USB clock gate and reset indices, and how the
USB host is mapped to a USB phy, for the newer chips.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 30 +++++++++++++--------------
 drivers/usb/host/ehci-sunxi.c                 |  9 +++++++-
 drivers/usb/host/ohci-sunxi.c                 |  9 +++++++-
 3 files changed, 30 insertions(+), 18 deletions(-)

Patch

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d328df9..2c82d0a 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -270,17 +270,18 @@  struct sunxi_ccm_reg {
 #define AXI_GATE_OFFSET_DRAM		0
 
 /* ahb_gate0 offsets */
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
+#define AHB_GATE_OFFSET_USB_OHCI3	31
+#define AHB_GATE_OFFSET_USB_OHCI2	30
+#define AHB_GATE_OFFSET_USB_OHCI1	29
+#define AHB_GATE_OFFSET_USB_OHCI0	28
+#define AHB_GATE_OFFSET_USB_EHCI3	27
+#define AHB_GATE_OFFSET_USB_EHCI2	26
+#define AHB_GATE_OFFSET_USB_EHCI1	25
+#define AHB_GATE_OFFSET_USB_EHCI0	24
+#else
 #define AHB_GATE_OFFSET_USB_OHCI1	30
 #define AHB_GATE_OFFSET_USB_OHCI0	29
-#ifdef CONFIG_MACH_SUNXI_H3_H5
-/*
- * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
- * them 0 - 2 like they were called on older SoCs.
- */
-#define AHB_GATE_OFFSET_USB_EHCI2	27
-#define AHB_GATE_OFFSET_USB_EHCI1	26
-#define AHB_GATE_OFFSET_USB_EHCI0	25
-#else
 #define AHB_GATE_OFFSET_USB_EHCI1	27
 #define AHB_GATE_OFFSET_USB_EHCI0	26
 #endif
@@ -339,13 +340,10 @@  struct sunxi_ccm_reg {
 #define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
 #define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
 #ifdef CONFIG_MACH_SUNXI_H3_H5
-/*
- * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call
- * them 0 - 2 like they were called on older SoCs.
- */
-#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17)
-#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18)
-#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19)
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
+#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18)
+#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19)
 #else
 #define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
 #define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
diff --git a/drivers/usb/host/ehci-sunxi.c b/drivers/usb/host/ehci-sunxi.c
index 6ecb7c4..f40228e 100644
--- a/drivers/usb/host/ehci-sunxi.c
+++ b/drivers/usb/host/ehci-sunxi.c
@@ -48,10 +48,17 @@  static int ehci_usb_probe(struct udevice *dev)
 #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
 	extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_OHCI0;
 #endif
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
+	/* Newer chips have a EHCI/OHCI host pair for OTG host mode */
+	priv->phy_index = ((uintptr_t)hccr - SUNXI_USB0_BASE) / BASE_DIST;
+#else
 	priv->phy_index = ((uintptr_t)hccr - SUNXI_USB1_BASE) / BASE_DIST;
+#endif
 	priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
 	extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
-	priv->phy_index++; /* Non otg phys start at 1 */
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
+	priv->phy_index++; /* older chips do not have EHCI with OTG */
+#endif
 
 	setbits_le32(&ccm->ahb_gate0,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);
diff --git a/drivers/usb/host/ohci-sunxi.c b/drivers/usb/host/ohci-sunxi.c
index 133774f..4b8a403 100644
--- a/drivers/usb/host/ohci-sunxi.c
+++ b/drivers/usb/host/ohci-sunxi.c
@@ -51,11 +51,18 @@  static int ohci_usb_probe(struct udevice *dev)
 	extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
 #endif
 	priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
+	/* Newer chips have a EHCI/OHCI host pair for OTG host mode */
+	priv->phy_index = ((uintptr_t)regs - (SUNXI_USB0_BASE + 0x400)) / BASE_DIST;
+#else
 	priv->phy_index = ((uintptr_t)regs - (SUNXI_USB1_BASE + 0x400)) / BASE_DIST;
+#endif
 	priv->ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
 	extra_ahb_gate_mask <<= priv->phy_index * AHB_CLK_DIST;
 	priv->usb_gate_mask <<= priv->phy_index;
-	priv->phy_index++; /* Non otg phys start at 1 */
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
+	priv->phy_index++; /* older chips do not have OHCI with OTG */
+#endif
 
 	setbits_le32(&ccm->ahb_gate0,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);