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[61.216.91.114]) by smtp.gmail.com with ESMTPSA id k80sm14337459pfh.30.2018.01.05.08.17.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 05 Jan 2018 08:17:08 -0800 (PST) From: Jun Nie To: jagannadh.teki@gmail.com, wens@csie.org, maxime.ripard@free-electrons.com, hdegoede@redhat.com Date: Sat, 6 Jan 2018 00:15:59 +0800 Message-Id: <1515168960-18960-8-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1515168960-18960-1-git-send-email-jun.nie@linaro.org> References: <1515168960-18960-1-git-send-email-jun.nie@linaro.org> Cc: u-boot@lists.denx.de Subject: [U-Boot] [[PATCH v2] 7/8] sunxi: usb_phy: setup USB PHY passby for USB0 on H3/H5/A64 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Chen-Yu Tsai On newer chips, there is a pair of EHCI/OHCI USB hosts for OTG host mode. USB PHY passby must be configured for its corresponding PHY. Signed-off-by: Chen-Yu Tsai --- arch/arm/mach-sunxi/usb_phy.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c index bcf5f15..4ae0a77 100644 --- a/arch/arm/mach-sunxi/usb_phy.c +++ b/arch/arm/mach-sunxi/usb_phy.c @@ -245,7 +245,12 @@ void sunxi_usb_phy_init(int index) sunxi_usb_phy_config(phy); - if (phy->id != 0) + /* + * Later SoCs such as the H3, H5, A64 have proper hosts for OTG. + * As such the passby settings need to be set for them as well. + */ + if (phy->id != 0 || IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5) || + IS_ENABLED(CONFIG_MACH_SUN50I)) sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN); #ifdef CONFIG_MACH_SUN8I_A83T