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Mon, 22 Oct 2012 20:57:40 +0900 (KST) Received: from hatim-linux.sisodomain.com ([107.108.73.95]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MCA006A7MH2ZQ10@mmp1.samsung.com> for patches@linaro.org; Mon, 22 Oct 2012 20:57:40 +0900 (KST) From: Hatim Ali To: u-boot@lists.denx.de Cc: sjg@chromium.org, promsoft@gmail.com, patches@linaro.org Subject: [PATCH 1/6 V7] EXYNOS5: Add pinmux support for SPI Date: Mon, 22 Oct 2012 17:22:04 +0530 Message-id: <1350906729-23749-2-git-send-email-hatim.rv@samsung.com> X-Mailer: git-send-email 1.7.2.3 In-reply-to: <1350906729-23749-1-git-send-email-hatim.rv@samsung.com> References: <1350906729-23749-1-git-send-email-hatim.rv@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrNLMWRmVeSWpSXmKPExsWyRsSkWnerSWuAQeNNTosph7+wODB63Lm2 hy2AMYrLJiU1J7MstUjfLoErY8quaewFf8QqpnU+ZWtgvCXUxcjJISFgInFgy1d2CFtM4sK9 9WxdjFwcQgJLGSUOLj3F2sXIAVa0YJcFRHwRo8T7C0dYoBwmiUM/V4F1swmoSax/3ckGYosI SEj86r/KCGIzC9hILOm5B2YLC1hLTFp1gxnEZhFQlbi+sQ2sl1fARaLpVSsjxBUKEq9urAWL cwq4Stzv7wA7QgioZn6vIkSrgMS3yYdYIG6Tldh0gBnkHAmBy2wSe5bNYIYYIylxcMUNlgmM wgsYGVYxiqYWJBcUJ6XnGuoVJ+YWl+al6yXn525iBIbg6X/PpHYwrmywOMQowMGoxMOrodAa IMSaWFZcmXuIUYKDWUmE94oYUIg3JbGyKrUoP76oNCe1+BCjD9AlE5mlRJPzgfGRVxJvaGxi bmpsamlkZGZqikNYSZy32SMlQEggPbEkNTs1tSC1CGYcEwenVAOjyzl7rbvpfWdb3e0vVbyu O8Nrc/mZzj9F/2l9wZ3KHCnXHQ1dZpyTXbXf/VN2ncMvs0WWuudStWxXyX8+92wO54sN5pFL i3p+CdX/FVG+edToac1y+z0qax1WKUpeM7VqYXtQ94pjW1JPhcuZ6XnKK2Y2B92u+8Cxc2Gt 9f4NRvaWZbFPvpgosRRnJBpqMRcVJwIAHqLlbm4CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupikeLIzCtJLcpLzFFi42I5/e+xgO4Wk9YAg02bLC2mHP7C4sDocefa HrYAxqgGRpuM1MSU1CKF1Lzk/JTMvHRbJe/geOd4UzMDQ11DSwtzJYW8xNxUWyUXnwBdt8wc oLFKCmWJOaVAoYDE4mIlfTtME0JD3HQtYBojdH1DguB6jAzQQMIaxowpu6axF/wRq5jW+ZSt gfGWUBcjB4eEgInEgl0WXYycQKaYxIV769m6GLk4hAQWMUq8v3CEBcphkjj0cxU7SBWbgJrE +tedbCC2iICExK/+q4wgNrOAjcSSnntgtrCAtcSkVTeYQWwWAVWJ6xvbwHp5BVwkml61MkJs U5B4dWMtWJxTwFXifn8HK8hBQkA183sVJzDyLmBkWMUomlqQXFCclJ5rqFecmFtcmpeul5yf u4kRHODPpHYwrmywOMQowMGoxMOrodAaIMSaWFZcmXuIUYKDWUmE94oYUIg3JbGyKrUoP76o NCe1+BCjD9BRE5mlRJPzgdGXVxJvaGxibmpsamliYWJmiUNYSZy32SMlQEggPbEkNTs1tSC1 CGYcEwenVAOjziWNpu2cDK33067dOGx0Se7CyxMNO50Cbv2oDs12MwqJ/xE0Y82n9EW/z6+6 fbTRRERA1LLazDVbx+BkitK8c1kMJ91lG+Y9M/cum/Yn6LjjiXaGYPmni19McytKUptsqr01 81ZP9sVDVUmtUYc/XQjivsfGGDJ15/77YYtsMyYpztB44yqvxFKckWioxVxUnAgA27W6Zp0C AAA= X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQn18upPPE6w2BQD2sOG+vbq7VlQwpvuyszx9/1r6obFl3tPyRjAOpPU8ws6bbRaH+wsl6N1 From: Rajeshwari Shinde This patch adds pinmux support for SPI channels Signed-off-by: Rajeshwari Shinde Signed-off-by: Hatim Ali Acked-by: Simon Glass --- Changes since v4: Fixed minor nits suggested by Simon Glass Changes since v5: No change Changes since v6: Incorporated review comments by Simon Glass & Minkyu Kang diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 5796d56..3ecbf7d 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -112,6 +112,7 @@ static int exynos5_mmc_config(int peripheral, int flags) s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); } + return 0; } @@ -230,6 +231,49 @@ static void exynos5_i2c_config(int peripheral, int flags) } } +void exynos5_spi_config(int peripheral) +{ + int cfg = 0, pin = 0, i; + struct s5p_gpio_bank *bank = NULL; + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + struct exynos5_gpio_part2 *gpio2 = + (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); + + switch (peripheral) { + case PERIPH_ID_SPI0: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI1: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 4; + break; + case PERIPH_ID_SPI2: + bank = &gpio1->b1; + cfg = GPIO_FUNC(0x5); + pin = 1; + break; + case PERIPH_ID_SPI3: + bank = &gpio2->f1; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI4: + for (i = 0; i < 2; i++) { + s5p_gpio_cfg_pin(&gpio2->f0, i + 2, GPIO_FUNC(0x4)); + s5p_gpio_cfg_pin(&gpio2->e0, i + 4, GPIO_FUNC(0x4)); + } + break; + } + if (peripheral != PERIPH_ID_SPI4) { + for (i = pin; i < pin + 4; i++) + s5p_gpio_cfg_pin(bank, i, cfg); + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -257,6 +301,13 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_I2C7: exynos5_i2c_config(peripheral, flags); break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + exynos5_spi_config(peripheral); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index 082611c..4054fb6 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -44,6 +44,11 @@ enum periph_id { PERIPH_ID_SDMMC3, PERIPH_ID_SDMMC4, PERIPH_ID_SROMC, + PERIPH_ID_SPI0, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, PERIPH_ID_UART0, PERIPH_ID_UART1, PERIPH_ID_UART2,