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[203.254.224.34]) by mx.google.com with ESMTP id n5si16044032paw.89.2012.10.22.23.48.45; Mon, 22 Oct 2012 23:48:45 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MCC00L8G2UKAMT0@mailout4.samsung.com>; Tue, 23 Oct 2012 15:48:44 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.125]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 55.F6.01231.CCD36805; Tue, 23 Oct 2012 15:48:44 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-e0-50863dcc4c12 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id E4.F6.01231.CCD36805; Tue, 23 Oct 2012 15:48:44 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MCC00CQ52Q0V720@mmp1.samsung.com>; Tue, 23 Oct 2012 15:48:44 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org Subject: [PATCH 8/9 V3] EXYNOS: Add clock for I2S Date: Tue, 23 Oct 2012 12:27:28 +0530 Message-id: <1350975449-27816-9-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1350975449-27816-1-git-send-email-rajeshwari.s@samsung.com> References: <1350975449-27816-1-git-send-email-rajeshwari.s@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrALMWRmVeSWpSXmKPExsWyRsSkVveMbVuAwYZZShYP199ksZhy+AuL A5PHnWt72AIYo7hsUlJzMstSi/TtErgy1h46z1SwxbhizZerTA2MO7S6GDk5JARMJBp6L7BA 2GISF+6tZwOxhQSWMkrcXJ0OU3P83WygGi6g+CJGiaPP7kA5E5kklpztZwSpYhMwkth6chqY LSIgIfGr/yqYzSwQI/F6/w+wqcIChhKXFq5jB7FZBFQlFj/YD7aZV8BD4tjePjaIbQoSx6Z+ ZQWxOQU8JYCuBqrhAFrmIbHvZClEq4DEt8mHwMISArISmw4wg5wjIXCbTWLP+t/MEGMkJQ6u uMEygVF4ASPDKkbR1ILkguKk9FxDveLE3OLSvHS95PzcTYzAYDz975nUDsaVDRaHGAU4GJV4 eC2OtAYIsSaWFVfmHmKU4GBWEuFtsGoLEOJNSaysSi3Kjy8qzUktPsToA3TJRGYp0eR8YKTk lcQbGpuYmxqbWhoZmZma4hBWEudt9kgJEBJITyxJzU5NLUgtghnHxMEp1cDodTw/4ffymIW1 n7w/uEh5qswM4EoPNSvbYee58iDTIxXP4Ny8oAlHLnoq3FL0mN/94PXb+Q5aB2/ptWUWL2Pg 4mGV/RYSdIh7BsuNmcZpH2wZDMLezv/p/2TqvBAbAbk9X351tHz1eX9YvGP7NDuzgyzMnvPW XM/Wad1b/nLV6uUubjpF8jpKLMUZiYZazEXFiQA+rItTcwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAIsWRmVeSWpSXmKPExsVy+t9jAd0ztm0BBi0XRS0err/JYjHl8BcW ByaPO9f2sAUwRjUw2mSkJqakFimk5iXnp2TmpdsqeQfHO8ebmhkY6hpaWpgrKeQl5qbaKrn4 BOi6ZeYAzVZSKEvMKQUKBSQWFyvp22GaEBripmsB0xih6xsSBNdjZIAGEtYwZqw9dJ6pYItx xZovV5kaGHdodTFyckgImEgcfzebBcIWk7hwbz1bFyMXh5DAIkaJo8/usEA4E5kklpztZwSp YhMwkth6chqYLSIgIfGr/yqYzSwQI/F6/w82EFtYwFDi0sJ17CA2i4CqxOIH+8E28Ap4SBzb 28cGsU1B4tjUr6wgNqeApwTQdUA1HEDLPCT2nSydwMi7gJFhFaNoakFyQXFSeq6hXnFibnFp Xrpecn7uJkZwsD+T2sG4ssHiEKMAB6MSD6/FkdYAIdbEsuLK3EOMEhzMSiK8DVZtAUK8KYmV ValF+fFFpTmpxYcYfYCOmsgsJZqcD4zEvJJ4Q2MTc1NjU0sTCxMzSxzCSuK8zR4pAUIC6Ykl qdmpqQWpRTDjmDg4pRoYpdP3fbKv3npihuG3rhnOgQyd6c6b/h2fLnA59O7jzsDuc8fDzfKW ugYLu5/SX3l2Y9gNsdWKH9zmhP2ZG3NiotI1t87lwUz7bhnVPaoSTErWfOZbfKlHtH7/n4r5 x63+imcv9tGe+URdUTDy2E92Xv16YckUx6MSp95M+T6Z8dOPebe+CoTrK7EUZyQaajEXFScC AL0KNLOjAgAA X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQk6rfxEXTrOH/thEtqPLJlyoKBmV3kHsvgG5HaJLKnunzCbVPlZPRB0zLGFsPnz9MWRl4vr This patch adds clock support for I2S Signed-off-by: R. Chandrasekar Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- Changes in V2: - None Changes in V3: - Changes clock function names as suggested by Minkyu Kang. arch/arm/cpu/armv7/exynos/clock.c | 120 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 3 + arch/arm/include/asm/arch-exynos/clock.h | 29 +++++++ 3 files changed, 152 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 4f3b451..5f7d884 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,6 +26,16 @@ #include #include +/* Epll Clock division values to achive different frequency output */ +static struct set_epll_con_val exynos5_epll_div[] = { + { 192000000, 0, 48, 3, 1, 0 }, + { 180000000, 0, 45, 3, 1, 0 }, + { 73728000, 1, 73, 3, 3, 47710 }, + { 67737600, 1, 90, 4, 3, 20762 }, + { 49152000, 0, 49, 3, 3, 9961 }, + { 45158400, 0, 45, 3, 3, 10381 }, + { 180633600, 0, 45, 3, 1, 10381 } +}; /* exynos4: return pll clock frequency */ static unsigned long exynos4_get_pll_clk(int pllreg) { @@ -732,6 +742,93 @@ static unsigned long exynos5_get_i2c_clk(void) return aclk_66; } +int exynos5_set_epll_clk(unsigned long rate) +{ + unsigned int epll_con, epll_con_k; + unsigned int i; + unsigned int lockcnt; + unsigned int start; + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + + epll_con = readl(&clk->epll_con0); + epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK << + EPLL_CON0_LOCK_DET_EN_SHIFT) | + EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT | + EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT | + EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT); + + for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) { + if (exynos5_epll_div[i].freq_out == rate) + break; + } + + if (i == ARRAY_SIZE(exynos5_epll_div)) + return -1; + + epll_con_k = exynos5_epll_div[i].k_dsm << 0; + epll_con |= exynos5_epll_div[i].en_lock_det << + EPLL_CON0_LOCK_DET_EN_SHIFT; + epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT; + epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT; + epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT; + + /* + * Required period ( in cycles) to genarate a stable clock output. + * The maximum clock time can be up to 3000 * PDIV cycles of PLLs + * frequency input (as per spec) + */ + lockcnt = 3000 * exynos5_epll_div[i].p_div; + + writel(lockcnt, &clk->epll_lock); + writel(epll_con, &clk->epll_con0); + writel(epll_con_k, &clk->epll_con1); + + start = get_timer(0); + + while (!(readl(&clk->epll_con0) & + (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) { + if (get_timer(start) > TIMEOUT_EPLL_LOCK) { + debug("%s: Timeout waiting for EPLL lock\n", __func__); + return -1; + } + } + return 0; +} + +void exynos5_set_i2s_clk_source(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + + clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK, + (CLK_SRC_SCLK_EPLL)); +} + +int exynos5_set_i2s_clk_prescaler(unsigned int src_frq, + unsigned int dst_frq) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned int div; + + if ((dst_frq == 0) || (src_frq == 0)) { + debug("%s: Invalid requency input for prescaler\n", __func__); + debug("src frq = %d des frq = %d ", src_frq, dst_frq); + return -1; + } + + div = (src_frq / dst_frq); + if (div > AUDIO_1_RATIO_MASK) { + debug("%s: Frequency ratio is out of range\n", __func__); + debug("src frq = %d des frq = %d ", src_frq, dst_frq); + return -1; + } + clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK, + (div & AUDIO_1_RATIO_MASK)); + return 0; +} + unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) @@ -803,3 +900,26 @@ void set_mipi_clk(void) if (cpu_is_exynos4()) exynos4_set_mipi_clk(); } + +int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) +{ + + if (cpu_is_exynos5()) + return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq); + else + return 0; +} + +void set_i2s_clk_source(void) +{ + if (cpu_is_exynos5()) + exynos5_set_i2s_clk_source(); +} + +int set_epll_clk(unsigned long rate) +{ + if (cpu_is_exynos5()) + return exynos5_set_epll_clk(rate); + else + return 0; +} diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 5529025..2bf2c10 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -38,5 +38,8 @@ void set_mmc_clk(int dev_index, unsigned int div); unsigned long get_lcd_clk(void); void set_lcd_clk(void); void set_mipi_clk(void); +void set_i2s_clk_source(void); +int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq); +int set_epll_clk(unsigned long rate); #endif diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index fce38ef..ff6781a 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -595,9 +595,38 @@ struct exynos5_clock { unsigned int pll_div2_sel; unsigned char res123[0xf5d8]; }; + +/* structure for epll configuration used in audio clock configuration */ +struct set_epll_con_val { + unsigned int freq_out; /* frequency out */ + unsigned int en_lock_det; /* enable lock detect */ + unsigned int m_div; /* m divider value */ + unsigned int p_div; /* p divider value */ + unsigned int s_div; /* s divider value */ + unsigned int k_dsm; /* k value of delta signal modulator */ +}; #endif #define MPLL_FOUT_SEL_SHIFT 4 +#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/ +#define TIMEOUT_EPLL_LOCK 1000 + +#define AUDIO_0_RATIO_MASK 0x0f +#define AUDIO_1_RATIO_MASK 0x0f + +#define AUDIO1_SEL_MASK 0xf +#define CLK_SRC_SCLK_EPLL 0x7 + +/* CON0 bit-fields */ +#define EPLL_CON0_MDIV_MASK 0x1ff +#define EPLL_CON0_PDIV_MASK 0x3f +#define EPLL_CON0_SDIV_MASK 0x7 +#define EPLL_CON0_MDIV_SHIFT 16 +#define EPLL_CON0_PDIV_SHIFT 8 +#define EPLL_CON0_SDIV_SHIFT 0 +#define EPLL_CON0_LOCK_DET_EN_SHIFT 28 +#define EPLL_CON0_LOCK_DET_EN_MASK 1 + #define MPLL_FOUT_SEL_MASK 0x1 #define BPLL_FOUT_SEL_SHIFT 0 #define BPLL_FOUT_SEL_MASK 0x1