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[81.169.180.215]) by mx.google.com with ESMTP id b22si1554338edn.176.2018.01.12.04.46.20; Fri, 12 Jan 2018 04:46:21 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=MTpMuXIS; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.denx.de (Postfix, from userid 105) id 90098C220B8; Fri, 12 Jan 2018 12:41:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8E1ADC221C3; Fri, 12 Jan 2018 12:40:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5065BC22140; Fri, 12 Jan 2018 12:40:37 +0000 (UTC) Received: from mail-wm0-f66.google.com (mail-wm0-f66.google.com [74.125.82.66]) by lists.denx.de (Postfix) with ESMTPS id 52125C22186 for ; Fri, 12 Jan 2018 12:40:33 +0000 (UTC) Received: by mail-wm0-f66.google.com with SMTP id 143so11750634wma.5 for ; Fri, 12 Jan 2018 04:40:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=w+zK1eWV5hBU6c/Zv9Z9lu/ZFoqHxc3b/EFH3dGFNHo=; b=MTpMuXISsx1Osl2pqv1FtQr0VAsQMR1wJx+HLpxubLYDtArM0mjnHyAx91cH/jJKwe uputCFYs2JQalUJwet2Z1k4v4q7nswrdSWx3Fn3fpwi52PwP3GmgvvXo4L/X6NMazvww eacO5e+smIeQkyIzpJBM+tYxE84ebyb/FFoyo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=w+zK1eWV5hBU6c/Zv9Z9lu/ZFoqHxc3b/EFH3dGFNHo=; b=Ls1x6FL4cQuhfOXnltM3RAzoHKAxvkLsBqxr3FpX4sqZ4AnhQt6IB7NaSGq7GtsOsi eJG98Jg/+g+qBmjq2N8+wF1iENPFWXY58Oh3QZ5CVQpFsS9XpU4tu7E7Q8gp+oeKoGfK 7lXT2jwA8Hax90hcTzkovS6lMJ/EdLTvDOavNxGrJRllRPxHa8iNXE8DnKqkVA/uiv+P 4Nw81r1WVHM63X0XQOFzl/6wmKar8UUjYwDBXNWg7nFa+2nFVkcjMBkc3NVK5FPK+K+W RELT/Z3xoBscxY58kuMiK7j8E7puaz2DId3Up0UxAuUW568hoDSVQzRbPrYy07okIAO8 tRRA== X-Gm-Message-State: AKwxytfBhbqvUti7Jov6O6vbszW+tt2cNNcGGzUlxd1lwHNxsYabhl86 S/cc4l2z9vAAfp2Qj4i6MXvTTMWC938= X-Received: by 10.80.245.172 with SMTP id u41mr16883235edm.163.1515760832755; Fri, 12 Jan 2018 04:40:32 -0800 (PST) Received: from localhost.localdomain ([109.255.42.2]) by smtp.gmail.com with ESMTPSA id w2sm13893585edb.4.2018.01.12.04.40.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 12 Jan 2018 04:40:32 -0800 (PST) From: Bryan O'Donoghue To: u-boot@lists.denx.de, brenomatheus@gmail.com Date: Fri, 12 Jan 2018 12:40:02 +0000 Message-Id: <1515760819-15116-9-git-send-email-bryan.odonoghue@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515760819-15116-1-git-send-email-bryan.odonoghue@linaro.org> References: <1515760819-15116-1-git-send-email-bryan.odonoghue@linaro.org> Cc: Fabio Estevam Subject: [U-Boot] [PATCH v6 08/25] arm: imx: hab: Add IVT header definitions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The various i.MX BootROMs containing the High Assurance Boot (HAB) block rely on a data structure called the Image Vector Table (IVT) to describe to the BootROM where to locate various data-structures used by HAB during authentication. This patch adds a definition of the IVT header for use in later patches, where we will break the current incorrect dependence on fixed offsets in favour of an IVT described parsing of incoming binaries. Signed-off-by: Bryan O'Donoghue Cc: Stefano Babic Cc: Fabio Estevam Cc: Peng Fan Cc: Albert Aribaud Cc: Sven Ebenfeld Cc: George McCollister Cc: Breno Matheus Lima Tested-by: Breno Lima Reviewed-by: Fabio Estevam --- arch/arm/include/asm/mach-imx/hab.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h index b2a8031..28cde38 100644 --- a/arch/arm/include/asm/mach-imx/hab.h +++ b/arch/arm/include/asm/mach-imx/hab.h @@ -10,6 +10,34 @@ #include +/* + * IVT header definitions + * Security Reference Manual for i.MX 7Dual and 7Solo Applications Processors, + * Rev. 0, 03/2017 + * Section : 6.7.1.1 + */ +#define IVT_HEADER_MAGIC 0xD1 +#define IVT_TOTAL_LENGTH 0x20 +#define IVT_HEADER_V1 0x40 +#define IVT_HEADER_V2 0x41 + +struct ivt_header { + uint8_t magic; + uint16_t length; + uint8_t version; +} __attribute__((packed)); + +struct ivt { + struct ivt_header hdr; /* IVT header above */ + uint32_t entry; /* Absolute address of first instruction */ + uint32_t reserved1; /* Reserved should be zero */ + uint32_t dcd; /* Absolute address of the image DCD */ + uint32_t boot; /* Absolute address of the boot data */ + uint32_t self; /* Absolute address of the IVT */ + uint32_t csf; /* Absolute address of the CSF */ + uint32_t reserved2; /* Reserved should be zero */ +}; + /* -------- start of HAB API updates ------------*/ /* The following are taken from HAB4 SIS */