[v10.5,11/20] target/arm: Align vector registers

Message ID	20180117161435.28981-12-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Wed, 17 Jan 2018 08:14:26 -0800 Message-Id: <20180117161435.28981-12-richard.henderson@linaro.org> In-Reply-To: <20180117161435.28981-1-richard.henderson@linaro.org> References: <20180117161435.28981-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v10.5 11/20] target/arm: Align vector registers Precedence: list Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org>
Series	tcg: generic vector operations \| expand [v10.5,00/20] tcg: generic vector operations [v10.5,01/20] tcg: Allow multiple word entries into the constant pool [v10.5,02/20] tcg: Add types and basic operations for host vectors [v10.5,03/20] tcg: Standardize integral arguments to expanders [v10.5,04/20] tcg: Add generic vector expanders [v10.5,05/20] tcg: Add generic vector ops for constant shifts [v10.5,06/20] tcg: Add generic vector ops for comparisons [v10.5,07/20] tcg: Add generic vector ops for multiplication [v10.5,08/20] tcg: Add generic helpers for saturating arithmetic [v10.5,09/20] tcg: Add generic vector helpers with a scalar operand [v10.5,10/20] tcg/optimize: Handle vector opcodes during optimize [v10.5,11/20] target/arm: Align vector registers [v10.5,12/20] target/arm: Use vector infrastructure for aa64 add/sub/logic [v10.5,13/20] target/arm: Use vector infrastructure for aa64 mov/not/neg [v10.5,14/20] target/arm: Use vector infrastructure for aa64 dup/movi [v10.5,15/20] target/arm: Use vector infrastructure for aa64 constant shifts [v10.5,16/20] target/arm: Use vector infrastructure for aa64 compares [v10.5,17/20] target/arm: Use vector infrastructure for aa64 multiplies [v10.5,18/20] target/arm: Use vector infrastructure for aa64 orr/bic immediate [v10.5,19/20] tcg/i386: Add vector operations [v10.5,20/20] tcg/aarch64: Add vector operations

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20180117161435.28981-12-richard.henderson@linaro.org

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From: Richard Henderson <richard.henderson@linaro.org>
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Date: Wed, 17 Jan 2018 08:14:26 -0800
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Subject: [Qemu-devel] [PATCH v10.5 11/20] target/arm: Align vector registers
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Cc: peter.maydell@linaro.org
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Series

tcg: generic vector operations | expand

Commit Message

Richard Henderson Jan. 17, 2018, 4:14 p.m. UTC

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-- 
2.14.3

Comments

Alex Bennée Jan. 26, 2018, 9:52 a.m. UTC | #1

Richard Henderson <richard.henderson@linaro.org> writes:

> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

> ---

>  target/arm/cpu.h | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)

>

> diff --git a/target/arm/cpu.h b/target/arm/cpu.h

> index 96316700dd..3ff4dea6b8 100644

> --- a/target/arm/cpu.h

> +++ b/target/arm/cpu.h

> @@ -492,7 +492,7 @@ typedef struct CPUARMState {

>           * the two execution states, and means we do not need to explicitly

>           * map these registers when changing states.

>           */

> -        float64 regs[64];

> +        float64 regs[64] QEMU_ALIGNED(16);


There is a minor conflict that needs to be fixed with the now merged: 3f68b8a5a6862f856524bb347bf348ae364dd43c
>

>          uint32_t xregs[16];

>          /* We store these fpcsr fields separately for convenience.  */



--
Alex Bennée

Richard Henderson Jan. 26, 2018, 4:43 p.m. UTC | #2

On 01/26/2018 01:52 AM, Alex Bennée wrote:
> 

> Richard Henderson <richard.henderson@linaro.org> writes:

> 

>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

>> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

>> ---

>>  target/arm/cpu.h | 2 +-

>>  1 file changed, 1 insertion(+), 1 deletion(-)

>>

>> diff --git a/target/arm/cpu.h b/target/arm/cpu.h

>> index 96316700dd..3ff4dea6b8 100644

>> --- a/target/arm/cpu.h

>> +++ b/target/arm/cpu.h

>> @@ -492,7 +492,7 @@ typedef struct CPUARMState {

>>           * the two execution states, and means we do not need to explicitly

>>           * map these registers when changing states.

>>           */

>> -        float64 regs[64];

>> +        float64 regs[64] QEMU_ALIGNED(16);

> 

> There is a minor conflict that needs to be fixed with the now merged: 3f68b8a5a6862f856524bb347bf348ae364dd43c



Already done in v11 which I posted last night.


r~

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 96316700dd..3ff4dea6b8 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -492,7 +492,7 @@  typedef struct CPUARMState {
          * the two execution states, and means we do not need to explicitly
          * map these registers when changing states.
          */
-        float64 regs[64];
+        float64 regs[64] QEMU_ALIGNED(16);
 
         uint32_t xregs[16];
         /* We store these fpcsr fields separately for convenience.  */

[v10.5,11/20] target/arm: Align vector registers

Commit Message

Comments

Patch