diff mbox series

[v2,16/16] target/arm: Add SVE state to TB->FLAGS

Message ID 20180119045438.28582-17-richard.henderson@linaro.org
State New
Headers show
Series target/arm: Prepatory work for SVE | expand

Commit Message

Richard Henderson Jan. 19, 2018, 4:54 a.m. UTC 
Add both SVE exception state and vector length.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

---
 target/arm/cpu.h    |  4 ++++
 target/arm/helper.c | 23 ++++++++++++++++++++++-
 2 files changed, 26 insertions(+), 1 deletion(-)

-- 
2.14.3

Comments

Peter Maydell Jan. 22, 2018, 2:40 p.m. UTC | #1 
On 19 January 2018 at 04:54, Richard Henderson
<richard.henderson@linaro.org> wrote:
> Add both SVE exception state and vector length.

>

> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


> @@ -11772,14 +11772,35 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,

>                            target_ulong *cs_base, uint32_t *pflags)

>  {

>      ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));

> +    int fp_el = fp_exception_el(env);

>      uint32_t flags;

>

>      if (is_a64(env)) {

> +        int sve_el = sve_exception_el(env);

> +        uint32_t zcr_len;

> +

>          *pc = env->pc;

>          flags = ARM_TBFLAG_AARCH64_STATE_MASK;

>          /* Get control bits for tagged addresses */

>          flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT);

>          flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT);

> +        flags |= sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT;

> +

> +        /* If SVE is disabled, but FP is enabled,

> +           then the effective len is 0.  */

> +        if (sve_el != 0 && fp_el == 0) {

> +            zcr_len = 0;

> +        } else {

> +            int highest_el = arm_highest_el(env);

> +            int current_el = arm_current_el(env);

> +            int i;

> +

> +            zcr_len = 0xf & (uint32_t)env->vfp.zcr_el[highest_el];

> +            for (i = highest_el - 1; i >= MAX(1, current_el); --i) {

> +                zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[i]);

> +            }


This loop also doesn't consider the case of EL3 implemented but
EL2 not, I think.

thanks
-- PMM
diff mbox series

Patch

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 2de1afb53a..d7208d56df 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2646,6 +2646,10 @@  static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
 #define ARM_TBFLAG_TBI0_MASK (0x1ull << ARM_TBFLAG_TBI0_SHIFT)
 #define ARM_TBFLAG_TBI1_SHIFT 1        /* TBI1 for EL0/1  */
 #define ARM_TBFLAG_TBI1_MASK (0x1ull << ARM_TBFLAG_TBI1_SHIFT)
+#define ARM_TBFLAG_SVEEXC_EL_SHIFT  2
+#define ARM_TBFLAG_SVEEXC_EL_MASK   (0x3 << ARM_TBFLAG_SVEEXC_EL_SHIFT)
+#define ARM_TBFLAG_ZCR_LEN_SHIFT    4
+#define ARM_TBFLAG_ZCR_LEN_MASK     (0xf << ARM_TBFLAG_ZCR_LEN_SHIFT)
 
 /* some convenience accessor macros */
 #define ARM_TBFLAG_AARCH64_STATE(F) \
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 44814af99b..6072634ca8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11772,14 +11772,35 @@  void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
                           target_ulong *cs_base, uint32_t *pflags)
 {
     ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
+    int fp_el = fp_exception_el(env);
     uint32_t flags;
 
     if (is_a64(env)) {
+        int sve_el = sve_exception_el(env);
+        uint32_t zcr_len;
+
         *pc = env->pc;
         flags = ARM_TBFLAG_AARCH64_STATE_MASK;
         /* Get control bits for tagged addresses */
         flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT);
         flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT);
+        flags |= sve_el << ARM_TBFLAG_SVEEXC_EL_SHIFT;
+
+        /* If SVE is disabled, but FP is enabled,
+           then the effective len is 0.  */
+        if (sve_el != 0 && fp_el == 0) {
+            zcr_len = 0;
+        } else {
+            int highest_el = arm_highest_el(env);
+            int current_el = arm_current_el(env);
+            int i;
+
+            zcr_len = 0xf & (uint32_t)env->vfp.zcr_el[highest_el];
+            for (i = highest_el - 1; i >= MAX(1, current_el); --i) {
+                zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[i]);
+            }
+        }
+        flags |= zcr_len << ARM_TBFLAG_ZCR_LEN_SHIFT;
     } else {
         *pc = env->regs[15];
         flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
@@ -11822,7 +11843,7 @@  void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
     if (arm_cpu_data_is_big_endian(env)) {
         flags |= ARM_TBFLAG_BE_DATA_MASK;
     }
-    flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT;
+    flags |= fp_el << ARM_TBFLAG_FPEXC_EL_SHIFT;
 
     if (arm_v7m_is_handler_mode(env)) {
         flags |= ARM_TBFLAG_HANDLER_MASK;