| Message ID | 20180123035349.24538-3-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Preparatory work for SVE | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/arm/cpu.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 1854fe51a8..3f4f6b6144 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -188,6 +188,13 @@ typedef struct ARMVectorReg { > uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); > } ARMVectorReg; > > +/* In AArch32 mode, predicate registers do not exist at all. */ > +#ifdef TARGET_AARCH64 > +typedef struct ARMPredicateReg { > + uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); > +} ARMPredicateReg; > +#endif > + > > typedef struct CPUARMState { > /* Regs for current mode. */ > @@ -515,6 +522,11 @@ typedef struct CPUARMState { > struct { > ARMVectorReg zregs[32]; > > +#ifdef TARGET_AARCH64 > + /* Store FFR as pregs[16] to make it easier to treat as any other. */ > + ARMPredicateReg pregs[17]; > +#endif > + > uint32_t xregs[16]; > /* We store these fpcsr fields separately for convenience. */ > int vec_len; -- Alex Bennée
On 23 January 2018 at 03:53, Richard Henderson <richard.henderson@linaro.org> wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/cpu.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 1854fe51a8..3f4f6b6144 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -188,6 +188,13 @@ typedef struct ARMVectorReg { > uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); > } ARMVectorReg; > > +/* In AArch32 mode, predicate registers do not exist at all. */ > +#ifdef TARGET_AARCH64 > +typedef struct ARMPredicateReg { > + uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); > +} ARMPredicateReg; > +#endif > + > > typedef struct CPUARMState { > /* Regs for current mode. */ > @@ -515,6 +522,11 @@ typedef struct CPUARMState { > struct { > ARMVectorReg zregs[32]; > > +#ifdef TARGET_AARCH64 > + /* Store FFR as pregs[16] to make it easier to treat as any other. */ > + ARMPredicateReg pregs[17]; > +#endif Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1854fe51a8..3f4f6b6144 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -188,6 +188,13 @@ typedef struct ARMVectorReg { uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); } ARMVectorReg; +/* In AArch32 mode, predicate registers do not exist at all. */ +#ifdef TARGET_AARCH64 +typedef struct ARMPredicateReg { + uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16); +} ARMPredicateReg; +#endif + typedef struct CPUARMState { /* Regs for current mode. */ @@ -515,6 +522,11 @@ typedef struct CPUARMState { struct { ARMVectorReg zregs[32]; +#ifdef TARGET_AARCH64 + /* Store FFR as pregs[16] to make it easier to treat as any other. */ + ARMPredicateReg pregs[17]; +#endif + uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ int vec_len;
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/cpu.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.14.3