| Message ID | 20180123035349.24538-4-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/arm: Preparatory work for SVE | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > Save the high parts of the Zregs and all of the Pregs. > The ZCR_ELx registers are migrated via the CP mechanism. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/arm/machine.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 53 insertions(+) > > diff --git a/target/arm/machine.c b/target/arm/machine.c > index cb0e1c92bb..2c8b43062f 100644 > --- a/target/arm/machine.c > +++ b/target/arm/machine.c > @@ -122,6 +122,56 @@ static const VMStateDescription vmstate_iwmmxt = { > } > }; > > +#ifdef TARGET_AARCH64 > +/* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, > + * and ARMPredicateReg is actively empty. This triggers errors > + * in the expansion of the VMSTATE macros. > + */ > + > +static bool sve_needed(void *opaque) > +{ > + ARMCPU *cpu = opaque; > + CPUARMState *env = &cpu->env; > + > + return arm_feature(env, ARM_FEATURE_SVE); > +} > + > +/* The first two words of each Zreg is stored in VFP state. */ > +static const VMStateDescription vmstate_zreg_hi_reg = { > + .name = "cpu/sve/zreg_hi", > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static const VMStateDescription vmstate_preg_reg = { > + .name = "cpu/sve/preg", > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static const VMStateDescription vmstate_sve = { > + .name = "cpu/sve", > + .version_id = 1, > + .minimum_version_id = 1, > + .needed = sve_needed, > + .fields = (VMStateField[]) { > + VMSTATE_STRUCT_ARRAY(env.vfp.zregs, ARMCPU, 32, 0, > + vmstate_zreg_hi_reg, ARMVectorReg), > + VMSTATE_STRUCT_ARRAY(env.vfp.pregs, ARMCPU, 17, 0, > + vmstate_preg_reg, ARMPredicateReg), > + VMSTATE_END_OF_LIST() > + } > +}; > +#endif /* AARCH64 */ > + > static bool m_needed(void *opaque) > { > ARMCPU *cpu = opaque; > @@ -586,6 +636,9 @@ const VMStateDescription vmstate_arm_cpu = { > &vmstate_pmsav7, > &vmstate_pmsav8, > &vmstate_m_security, > +#ifdef TARGET_AARCH64 > + &vmstate_sve, > +#endif > NULL > } > }; -- Alex Bennée
On 23 January 2018 at 03:53, Richard Henderson <richard.henderson@linaro.org> wrote: > Save the high parts of the Zregs and all of the Pregs. > The ZCR_ELx registers are migrated via the CP mechanism. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > target/arm/machine.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 53 insertions(+) > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
diff --git a/target/arm/machine.c b/target/arm/machine.c index cb0e1c92bb..2c8b43062f 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -122,6 +122,56 @@ static const VMStateDescription vmstate_iwmmxt = { } }; +#ifdef TARGET_AARCH64 +/* The expression ARM_MAX_VQ - 2 is 0 for pure AArch32 build, + * and ARMPredicateReg is actively empty. This triggers errors + * in the expansion of the VMSTATE macros. + */ + +static bool sve_needed(void *opaque) +{ + ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; + + return arm_feature(env, ARM_FEATURE_SVE); +} + +/* The first two words of each Zreg is stored in VFP state. */ +static const VMStateDescription vmstate_zreg_hi_reg = { + .name = "cpu/sve/zreg_hi", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT64_SUB_ARRAY(d, ARMVectorReg, 2, ARM_MAX_VQ - 2), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_preg_reg = { + .name = "cpu/sve/preg", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT64_ARRAY(p, ARMPredicateReg, 2 * ARM_MAX_VQ / 8), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_sve = { + .name = "cpu/sve", + .version_id = 1, + .minimum_version_id = 1, + .needed = sve_needed, + .fields = (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(env.vfp.zregs, ARMCPU, 32, 0, + vmstate_zreg_hi_reg, ARMVectorReg), + VMSTATE_STRUCT_ARRAY(env.vfp.pregs, ARMCPU, 17, 0, + vmstate_preg_reg, ARMPredicateReg), + VMSTATE_END_OF_LIST() + } +}; +#endif /* AARCH64 */ + static bool m_needed(void *opaque) { ARMCPU *cpu = opaque; @@ -586,6 +636,9 @@ const VMStateDescription vmstate_arm_cpu = { &vmstate_pmsav7, &vmstate_pmsav8, &vmstate_m_security, +#ifdef TARGET_AARCH64 + &vmstate_sve, +#endif NULL } };
Save the high parts of the Zregs and all of the Pregs. The ZCR_ELx registers are migrated via the CP mechanism. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/machine.c | 53 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) -- 2.14.3