From patchwork Thu Jan 25 10:51:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 125788 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1028031ljf; Thu, 25 Jan 2018 02:56:11 -0800 (PST) X-Google-Smtp-Source: AH8x227TDzo83ZcyJYpBu1hMp4nsSoMC5rZ+sKNMgJTUUwazDQq9CYOE//Ja4HuUgk5PffOy65rC X-Received: by 10.80.216.143 with SMTP id p15mr18748444edj.294.1516877771482; Thu, 25 Jan 2018 02:56:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516877771; cv=none; d=google.com; s=arc-20160816; b=GF81EMlddvcw2AUjQdh/p5TJ0yzFg1/ld89HzJ3rSRNOq7J3MF98tciixSTbUcz45x jEY5siGZ2R05yxp9gxKf6NoGWVYgYAVY6hZYaVR5//v8sUmFmg5onrN4RNAL/mKw/uM6 Ac+FIW2+HF4Wi9N2hHNGN8HKP8oBAi89IcC0x+YM4K441wPn4iSAFQrpapjeS73HbhUG h9PgUjEpAa56a7cs6YkLvFQvDqsQW4P0ib5qpJYrJ/36W918ycvWjtBYudDhH2Zz3CwF zaJzaimYxr0o2kobmIleaf8+PJwyx2aKBOHv3Toxbnf7QB4mfw2NKSLdl2pay1VdRc1x jthA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=6aywy+Vr4ShYsX5fOcT1iRMSpsaIRGe4qVhqaxZQrdI=; b=i2UbeWU/+mVkDjuozM0sYS7wAMMe/MTCd2CJWX/eWMYXEK95kapfZNijT9T+iADBbE W2mTEURxgmPR1k7Gn1zFORDixeFH3GfhB2iu7nFJDbOVAtaq/1gsIC9MRygimh0GbP4v BWE2/gxWU90oQGmdVsZ4K+oF5Y712i7I3G7MVvgWFNtqCxFfjxviRjYJU99ZG5IWN+gC /MXsFvpPXYNTCf3m2rwsY5JApzc6QnVy5JzEOeTqS+BPBd3ojWj8rKZu2sHPEpEHFRfL eBxQtA88I6B4TcNpexzmfk8HFzyxrG9mOTXhXbs+PUTUuhFTdJUBDof8MA4EkFUs3B9U ZGGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=FlNNGZkr; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id n39si1938268edd.202.2018.01.25.02.56.11; Thu, 25 Jan 2018 02:56:11 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=FlNNGZkr; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 2A7EEC223A5; Thu, 25 Jan 2018 10:54:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DB0D5C223C9; Thu, 25 Jan 2018 10:52:30 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6D7BDC22397; Thu, 25 Jan 2018 10:52:13 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id A0629C223B3 for ; Thu, 25 Jan 2018 10:52:09 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0PAq69g013505; Thu, 25 Jan 2018 04:52:06 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1516877526; bh=pHcMGHNYFgx2VuJijjkVjh5vqIwVrdTyMC8X/Gjrqyk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=FlNNGZkrWaoYKI1lHZmFjdg3/k3c+5vRmwq33zwZBIPW8A4d4QAX/amHRJ46y4tuf t3Zp6vEguG4ahXsHo2/P3UhFor6PxvCYN9sUzZiothdjmwuLqZ3fQfXz/xuOldDeXf UQhjqiwviqiz9gWjWzh+kKdWQXyBvwnvUomS4X5w= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0PAq6nM004527; Thu, 25 Jan 2018 04:52:06 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 25 Jan 2018 04:52:06 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 25 Jan 2018 04:52:06 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0PAq5m7029051; Thu, 25 Jan 2018 04:52:06 -0600 From: Jean-Jacques Hiblot To: , , , Date: Thu, 25 Jan 2018 11:51:33 +0100 Message-ID: <1516877510-14863-8-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516877510-14863-1-git-send-email-jjhiblot@ti.com> References: <1516877510-14863-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 07/24] mmc: omap_hsmmc: Workaround for errata id i802 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I According to errata i802, DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure. The DCRC interrupt, occurs when the last tuning block fails (the last ratio tested). The delay from CRC check until the interrupt is asserted is bigger than the delay until assertion of the tuning end flag. Assertion of tuning end flag is what masks the interrupts. Because of this race, an erroneous DCRC interrupt occurs. The suggested workaround is to disable DCRC interrupts during the tuning procedure which is implemented here. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/omap_mmc.h | 4 ++++ drivers/mmc/omap_hsmmc.c | 26 ++++++++++++++++++++++---- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 0293281..0893844 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -219,6 +219,10 @@ struct omap_hsmmc_plat { #define mmc_reg_out(addr, mask, val)\ writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) +#define INT_EN_MASK (IE_BADA | IE_CERR | IE_DEB | IE_DCRC |\ + IE_DTO | IE_CIE | IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO |\ + IE_BRR | IE_BWR | IE_TC | IE_CC) + int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max, int cd_gpio, int wp_gpio); diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index fb29a08..3cfd062 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -476,6 +476,25 @@ tuning_error: #endif #endif +static void mmc_enable_irq(struct mmc *mmc, struct mmc_cmd *cmd) +{ + struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); + struct hsmmc *mmc_base = priv->base_addr; + u32 irq_mask = INT_EN_MASK; + + /* + * TODO: Errata i802 indicates only DCRC interrupts can occur during + * tuning procedure and DCRC should be disabled. But see occurences + * of DEB, CIE, CEB, CCRC interupts during tuning procedure. These + * interrupts occur along with BRR, so the data is actually in the + * buffer. It has to be debugged why these interrutps occur + */ + if (cmd && mmc_is_tuning_cmd(cmd->cmdidx)) + irq_mask &= ~(IE_DEB | IE_DCRC | IE_CIE | IE_CEB | IE_CCRC); + + writel(irq_mask, &mmc_base->ie); +} + static int omap_hsmmc_init_setup(struct mmc *mmc) { struct omap_hsmmc_data *priv = omap_hsmmc_get_data(mmc); @@ -542,10 +561,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); - writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | - IE_CEB | IE_CCRC | IE_ADMAE | IE_CTO | IE_BRR | IE_BWR | IE_TC | - IE_CC, &mmc_base->ie); - + mmc_enable_irq(mmc, NULL); mmc_init_stream(mmc_base); return 0; @@ -810,6 +826,8 @@ static int omap_hsmmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, #endif } + mmc_enable_irq(mmc, cmd); + writel(cmd->cmdarg, &mmc_base->arg); udelay(20); /* To fix "No status update" error on eMMC */ writel((cmd->cmdidx << 24) | flags, &mmc_base->cmd);