From patchwork Thu Jan 25 10:51:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Jacques Hiblot X-Patchwork-Id: 125795 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp1030964ljf; Thu, 25 Jan 2018 03:01:41 -0800 (PST) X-Google-Smtp-Source: AH8x227m/z0/8OXFeq305kabRMlLp3Q3mjSvz+6z/XRptcxDm6RG2FYw0pAmViX6P8611+hYSz1Y X-Received: by 10.80.175.162 with SMTP id h31mr29274269edd.48.1516878100909; Thu, 25 Jan 2018 03:01:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516878100; cv=none; d=google.com; s=arc-20160816; b=coiwRxhX1Uj7MaV4KURDgCQDXtmAmrjpeuRAbM6PfTu+0zHKfPvCycDf9JXUWsgujc 7GOcK1lwScbXFV2U3vmbGmmcGQBs7KMYs5A+yWIOki1y380xG+RzGKM8E15YVheh0EOQ rqKREQjZrUEADyO0/jWUZjG7GcOgEXdoL4/Yl2VQmwocwAXKYxxJg1Xqr+4NFz9D8TFv UUF35/oFNeHw6MObmFKhc+TbGKHFLKe8bjyCFdeSU72ZDgguNuFXzrxEUgfapS5oUSfa ZGvNcBcYWsf2Boc0kIEGjiexCgrtRrn6xQx8X6wsUUja/r7mbi03vF2tUjleVJrQXDtp BH6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=ooU95U+rNDeS0y79BxsTN/Yc6ybz8UB0ThVAg5bGW4U=; b=ofPVcnPj+bJy85g+HO3BlMZ+kn5KcrGLLpqbELSN9LFxHjaomcHzlYb+WXdOKfuLFY junm1f6IVZPvQL90b8xw/0hXEml8K9s72kZ0TNgFiguqaSD7XksGIYqmBwAMt4vwL7nH HdUgsZiJqoKnhMefYIG/MIh4lYtvH7vXjBU6JLBt2ZivxanULdcAmiVJbnswVUDlplD9 DtK46Q46q0howuj4MSkO+yRbDMTO/nqu89/vC1a2ZlVPg458xlvgH782lVEqsaloYek+ /PmJ43d3FtGlAPxNvTkYykEietNXmGaoQiUXKI1rpX/kHi/56kwJVTtidT6vychAuygh D20Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=XbX54IYd; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id i20si1758112ede.65.2018.01.25.03.01.40; Thu, 25 Jan 2018 03:01:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=XbX54IYd; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 6C98AC223E8; Thu, 25 Jan 2018 10:54:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 88392C223D8; Thu, 25 Jan 2018 10:52:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 854E6C223C3; Thu, 25 Jan 2018 10:52:10 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id 13035C223B7 for ; Thu, 25 Jan 2018 10:52:06 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0PAq4xu013493; Thu, 25 Jan 2018 04:52:04 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1516877524; bh=QVa0SnzCaM+eUXtHAbKeYWyEDZDlK+g+rhD5prI3P/A=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=XbX54IYdzFg3IbgFLxn89JexnJUiCOvZtCeOPHsOMC6JoM3d8Lp4QJSt4YtXCOBMm MmvTITIUIftX9J4cptq4A1cgjTn/+cPo8JGCpkI4DPu8REGmKOUjGjVXklxCScU0lc 40qJxcT0pVhdCbyRKT3kDFAOmyzG5hUPd4PUTP+g= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0PAq4ur020239; Thu, 25 Jan 2018 04:52:04 -0600 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 25 Jan 2018 04:52:03 -0600 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 25 Jan 2018 04:52:03 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0PAq3ZA004893; Thu, 25 Jan 2018 04:52:03 -0600 From: Jean-Jacques Hiblot To: , , , Date: Thu, 25 Jan 2018 11:51:31 +0100 Message-ID: <1516877510-14863-6-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1516877510-14863-1-git-send-email-jjhiblot@ti.com> References: <1516877510-14863-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 05/24] mmc: omap_hsmmc: Enable DDR mode support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I In order to enable DDR mode, Dual Data Rate mode bit has to be set in MMCHS_CON register. Set it here. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- arch/arm/include/asm/omap_mmc.h | 1 + drivers/mmc/omap_hsmmc.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h index 3f94f2e..341a2e2 100644 --- a/arch/arm/include/asm/omap_mmc.h +++ b/arch/arm/include/asm/omap_mmc.h @@ -89,6 +89,7 @@ struct omap_hsmmc_plat { #define WPP_ACTIVEHIGH (0x0 << 8) #define RESERVED_MASK (0x3 << 9) #define CTPL_MMC_SD (0x0 << 11) +#define DDR (0x1 << 19) #define DMA_MASTER (0x1 << 20) #define BLEN_512BYTESLEN (0x200 << 0) #define NBLK_STPCNT (0x0 << 16) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index a65005f..5f5fd90 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -271,6 +271,11 @@ static void omap_hsmmc_set_timing(struct mmc *mmc) val &= ~AC12_UHSMC_MASK; priv->mode = mmc->selected_mode; + if (mmc_is_mode_ddr(priv->mode)) + writel(readl(&mmc_base->con) | DDR, &mmc_base->con); + else + writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con); + switch (priv->mode) { case MMC_HS_200: case UHS_SDR104: