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[81.169.180.215]) by mx.google.com with ESMTP id z12si2988812edm.176.2018.01.25.13.47.11; Thu, 25 Jan 2018 13:47:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=NO7Y+zf6; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id C4C27C2232F; Thu, 25 Jan 2018 21:46:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 054FFC222BF; Thu, 25 Jan 2018 21:46:29 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 04F28C21D9F; Thu, 25 Jan 2018 21:46:26 +0000 (UTC) Received: from lelnx194.ext.ti.com (lelnx194.ext.ti.com [198.47.27.80]) by lists.denx.de (Postfix) with ESMTPS id D3098C21D9F for ; Thu, 25 Jan 2018 21:46:24 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0PLk0DD011450; Thu, 25 Jan 2018 15:46:00 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1516916760; bh=rXlrQwugHbnQMCZSRqMJSxJ0M7CoTjXuGIx/XcmrfFw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NO7Y+zf6alBRfFP/uBctONALZflEwMsf7/yfceRDzJd5j+K+A81x/i2CBad/bV0tP 1NYfFpr3lsiPfntXu/V2eLbiNEfp3WDZ6nTex7jJ7rC8ZTi/nio8uidyfLrc5KWEF3 U4R4eyc8U1E024vNpbK1cUwKEIYVOBySUf/SHA7U= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0PLk0Wt022900; Thu, 25 Jan 2018 15:46:00 -0600 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Thu, 25 Jan 2018 15:46:00 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Thu, 25 Jan 2018 15:46:00 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0PLk0Vs007092; Thu, 25 Jan 2018 15:46:00 -0600 From: Nishanth Menon To: Tom Rini Date: Thu, 25 Jan 2018 15:45:59 -0600 Message-ID: <20180125214559.27570-3-nm@ti.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180125214559.27570-1-nm@ti.com> References: <20180125214559.27570-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Russell King , u-boot@lists.denx.de, Ard Biesheuvel , Marc Zyngier , Catalin Marinas , Will Deacon , Tony Lindgren , Andre Przywara , Robin Murphy Subject: [U-Boot] [RFC PATCH 2/2] ARM: Introduce ability to enable invalidate of BTB on Cortex-A15 for CVE-2017-5715 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" As recommended by Arm in [1], ACR needs to be set[2] to enable invalidation of BTB. This has to be enabled unconditionally for ICIALLU to be functional on Cortex-A15 processors. Provide a config option for platforms to enable this option based on impact analysis for products. NOTE: This patch in itself is NOT the final solution, this requires: a) Implementation of v7_arch_cp15_set_acr on SoCs which may not provide direct access to ACR register. b) Operating Systems such as Linux to provide adequate workaround in the right locations. [1] https://developer.arm.com/support/security-update [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438c/BABGHIBG.html Cc: Marc Zyngier Cc: Russell King Cc: Tony Lindgren Cc: Robin Murphy Cc: Florian Fainelli Cc: Catalin Marinas Cc: Will Deacon Cc: Christoffer Dall Cc: Andre Przywara Cc: Ard Biesheuvel Cc: Tom Rini Cc: Michael Nazzareno Trimarchi Signed-off-by: Nishanth Menon --- arch/arm/Kconfig | 4 ++++ arch/arm/cpu/armv7/start.S | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c2ac0fef9d0c..116cee559ca4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -87,6 +87,7 @@ config THUMB2_KERNEL # CONFIG_ARM_ERRATA_798870 # CONFIG_ARM_ERRATA_801819 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715 +# CONFIG_ARM_CORTEX_A15_CVE_2017_5715 config ARM_ERRATA_430973 bool @@ -160,6 +161,9 @@ config ARM_ERRATA_855873 config ARM_CORTEX_A8_CVE_2017_5715 bool +config ARM_CORTEX_A15_CVE_2017_5715 + bool + config CPU_ARM720T bool select SYS_CACHE_SHIFT_5 diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 64c5d7598dea..4835316bb37e 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -238,6 +238,14 @@ skip_errata_798870: skip_errata_801819: #endif +#ifdef CONFIG_ARM_CORTEX_A15_CVE_2017_5715 + mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register + orr r0, r0, #1 << 0 @ Enable invalidates of BTB + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_acr + pop {r1-r5} @ Restore the cpu info - fall through +#endif + #ifdef CONFIG_ARM_ERRATA_454179 mrc p15, 0, r0, c1, c0, 1 @ Read ACR