Message ID | 20180128231528.22719-33-richard.henderson@linaro.org |
---|---|
State | Accepted |
Commit | 46559e8184b23e539912bb78764e662b5eabb537 |
Headers | show
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[174.21.6.47]) by smtp.gmail.com with ESMTPSA id r27sm26949344pfj.75.2018.01.28.15.16.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 28 Jan 2018 15:16:19 -0800 (PST) From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Sun, 28 Jan 2018 15:15:17 -0800 Message-Id: <20180128231528.22719-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180128231528.22719-1-richard.henderson@linaro.org> References: <20180128231528.22719-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PULL v4 32/43] target/hppa: Only use EXCP_DTLB_MISS X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+patch=linaro.org@nongnu.org> |
Series |
hppa-softmmu
|
expand
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diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index a34c64cc4a..08a4eb2480 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -96,7 +96,9 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, if (ent == NULL || !ent->entry_valid) { phys = 0; prot = 0; - ret = (type & PAGE_EXEC ? EXCP_ITLB_MISS : EXCP_DTLB_MISS); + /* ??? Unconditionally report data tlb miss, + even if this is an instruction fetch. */ + ret = EXCP_DTLB_MISS; goto egress; }
Unknown why this works, but if we return EXCP_ITLB_MISS we will triple-fault the first userland instruction fetch. Is it something to do with having a combined I/DTLB? Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/hppa/mem_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -- 2.14.3