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[81.169.180.215]) by mx.google.com with ESMTP id f35si322386edd.85.2018.01.30.07.09.37; Tue, 30 Jan 2018 07:09:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=IyzysEvN; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 1311BC21EAE; Tue, 30 Jan 2018 15:06:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B521BC21E3E; Tue, 30 Jan 2018 15:02:45 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A48D7C21E92; Tue, 30 Jan 2018 15:02:24 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id C02A0C21E64 for ; Tue, 30 Jan 2018 15:02:19 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w0UF2IY5005657; Tue, 30 Jan 2018 09:02:18 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517324538; bh=STKFg1/ZjC+tN/XQHNFmINnCzvGfoWHfGi5MiNVvLnA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IyzysEvNm5llUljCAU/RT47ZnyLnv7hwlMwqf6jJ/DnuOIoozIHGN/Pt0+Xnjh4BT L3sRSU68fqVf3/0/zom6/6Hr5JJv6QDNGsH1dNRCkprlcKeXAPwxvrzgTxeMrnSG/J txCmONTTaYNp2JrmcTk5eiHkCG14uWLUBwtW7340= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2IGb001573; Tue, 30 Jan 2018 09:02:18 -0600 Received: from DFLE108.ent.ti.com (10.64.6.29) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Tue, 30 Jan 2018 09:02:17 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Tue, 30 Jan 2018 09:02:17 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w0UF2H9Q028028; Tue, 30 Jan 2018 09:02:17 -0600 From: Jean-Jacques Hiblot To: , , , Date: Tue, 30 Jan 2018 16:01:45 +0100 Message-ID: <1517324513-13875-17-git-send-email-jjhiblot@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> References: <1517324513-13875-1-git-send-email-jjhiblot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 16/24] mmc: omap_hsmmc: allow mmc clock to be gated X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Kishon Vijay Abraham I mmc core has defined a new parameter *clk_disable* to gate the clock. Disable the clock here if *clk_disable* is set. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Jean-Jacques Hiblot --- Changes in v3: None drivers/mmc/omap_hsmmc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index 71608d1..0e80420 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -1207,6 +1207,7 @@ static int omap_hsmmc_set_ios(struct udevice *dev) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct mmc *mmc = upriv->mmc; #endif + struct hsmmc *mmc_base = priv->base_addr; if (priv->bus_width != mmc->bus_width) omap_hsmmc_set_bus_width(mmc); @@ -1214,6 +1215,11 @@ static int omap_hsmmc_set_ios(struct udevice *dev) if (priv->clock != mmc->clock) omap_hsmmc_set_clock(mmc); + if (mmc->clk_disable) + omap_hsmmc_stop_clock(mmc_base); + else + omap_hsmmc_start_clock(mmc_base); + #if CONFIG_IS_ENABLED(DM_MMC) if (priv->mode != mmc->selected_mode) omap_hsmmc_set_timing(mmc);